Searched refs:mmSDMA0_GFX_RB_WPTR_HI (Results 1 – 9 of 9) sorted by relevance
| /linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/sdma0/ |
| D | sdma0_4_1_offset.h | 216 #define mmSDMA0_GFX_RB_WPTR_HI … macro
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| D | sdma0_4_0_offset.h | 220 #define mmSDMA0_GFX_RB_WPTR_HI 0x0086 macro
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| D | sdma0_4_2_2_offset.h | 220 #define mmSDMA0_GFX_RB_WPTR_HI … macro
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| D | sdma0_4_2_offset.h | 216 #define mmSDMA0_GFX_RB_WPTR_HI … macro
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| /linux-5.19.10/drivers/gpu/drm/amd/amdgpu/ |
| D | sdma_v5_2.c | 274 wptr = RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)); in sdma_v5_2_ring_get_wptr()
319 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI), in sdma_v5_2_ring_set_wptr()
642 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0); in sdma_v5_2_gfx_resume()
676 … WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2)); in sdma_v5_2_gfx_resume()
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| D | sdma_v5_0.c | 373 wptr = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)); in sdma_v5_0_ring_get_wptr()
418 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI), in sdma_v5_0_ring_set_wptr()
741 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0); in sdma_v5_0_gfx_resume()
778 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), in sdma_v5_0_gfx_resume()
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| D | sdma_v4_0.c | 748 wptr = RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI); in sdma_v4_0_ring_get_wptr()
795 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI, in sdma_v4_0_ring_set_wptr()
1189 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_HI, 0); in sdma_v4_0_gfx_resume()
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| /linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| D | gc_10_1_0_offset.h | 214 #define mmSDMA0_GFX_RB_WPTR_HI … macro
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| D | gc_10_3_0_offset.h | 200 #define mmSDMA0_GFX_RB_WPTR_HI … macro
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