Searched refs:mmSDMA0_F32_CNTL (Results 1 – 16 of 16) sorted by relevance
| /linux-5.19.10/drivers/gpu/drm/amd/amdgpu/ |
| D | sdma_v2_4.c | 395 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); in sdma_v2_4_enable()
400 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl); in sdma_v2_4_enable()
974 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); in sdma_v2_4_soft_reset()
976 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); in sdma_v2_4_soft_reset()
981 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); in sdma_v2_4_soft_reset()
983 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); in sdma_v2_4_soft_reset()
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| D | cik_sdma.c | 417 me_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); in cik_sdma_enable()
422 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], me_cntl); in cik_sdma_enable()
1081 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); in cik_sdma_soft_reset()
1083 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); in cik_sdma_soft_reset()
1087 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); in cik_sdma_soft_reset()
1089 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); in cik_sdma_soft_reset()
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| D | sdma_v5_2.c | 594 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); in sdma_v5_2_enable()
596 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl); in sdma_v5_2_enable()
729 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); in sdma_v5_2_gfx_resume()
731 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp); in sdma_v5_2_gfx_resume()
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| D | sdma_v5_0.c | 694 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); in sdma_v5_0_enable()
696 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl); in sdma_v5_0_enable()
831 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); in sdma_v5_0_gfx_resume()
833 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp); in sdma_v5_0_gfx_resume()
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| D | sdma_v4_0.c | 1141 f32_cntl = RREG32_SDMA(i, mmSDMA0_F32_CNTL); in sdma_v4_0_enable()
1143 WREG32_SDMA(i, mmSDMA0_F32_CNTL, f32_cntl); in sdma_v4_0_enable()
1508 temp = RREG32_SDMA(i, mmSDMA0_F32_CNTL); in sdma_v4_0_start()
1510 WREG32_SDMA(i, mmSDMA0_F32_CNTL, temp); in sdma_v4_0_start()
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| D | sdma_v3_0.c | 630 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); in sdma_v3_0_enable()
635 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl); in sdma_v3_0_enable()
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| /linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/sdma0/ |
| D | sdma0_4_1_offset.h | 96 #define mmSDMA0_F32_CNTL … macro
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| D | sdma0_4_0_offset.h | 98 #define mmSDMA0_F32_CNTL 0x002a macro
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| D | sdma0_4_2_2_offset.h | 98 #define mmSDMA0_F32_CNTL … macro
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| D | sdma0_4_2_offset.h | 98 #define mmSDMA0_F32_CNTL … macro
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| /linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/oss/ |
| D | oss_2_4_d.h | 174 #define mmSDMA0_F32_CNTL 0x3412 macro
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| D | oss_3_0_1_d.h | 172 #define mmSDMA0_F32_CNTL 0x3412 macro
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| D | oss_2_0_d.h | 237 #define mmSDMA0_F32_CNTL 0x3412 macro
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| D | oss_3_0_d.h | 309 #define mmSDMA0_F32_CNTL 0x3412 macro
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| /linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| D | gc_10_1_0_offset.h | 73 #define mmSDMA0_F32_CNTL … macro
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| D | gc_10_3_0_offset.h | 78 #define mmSDMA0_F32_CNTL … macro
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