Searched refs:mmPWR_MISC_CNTL_STATUS (Results 1 – 5 of 5) sorted by relevance
| /linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/pwr/ |
| D | pwr_10_0_offset.h | 24 #define mmPWR_MISC_CNTL_STATUS … macro
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| /linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/smuio/ |
| D | smuio_12_0_0_offset.h | 27 #define mmPWR_MISC_CNTL_STATUS … macro
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| /linux-5.19.10/drivers/gpu/drm/amd/pm/swsmu/smu12/ |
| D | smu_v12_0.c | 54 #undef mmPWR_MISC_CNTL_STATUS
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| /linux-5.19.10/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| D | smu10_hwmgr.c | 340 reg = RREG32_SOC15(PWR, 0, mmPWR_MISC_CNTL_STATUS); in smu10_is_gfx_on()
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| /linux-5.19.10/drivers/gpu/drm/amd/amdgpu/ |
| D | gfx_v9_0.c | 2849 default_data = data = RREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS)); in pwr_10_0_gfxip_control_over_cgpg()
2854 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data); in pwr_10_0_gfxip_control_over_cgpg()
2860 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data); in pwr_10_0_gfxip_control_over_cgpg()
2865 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data); in pwr_10_0_gfxip_control_over_cgpg()
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