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Searched refs:mmPHYPLLF_PIXCLK_RESYNC_CNTL_BASE_IDX (Results 1 – 4 of 4) sorted by relevance

/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_1_0_offset.h569 #define mmPHYPLLF_PIXCLK_RESYNC_CNTL_BASE_IDX … macro
Ddcn_2_0_0_offset.h207 #define mmPHYPLLF_PIXCLK_RESYNC_CNTL_BASE_IDX … macro
Ddcn_3_0_0_offset.h188 #define mmPHYPLLF_PIXCLK_RESYNC_CNTL_BASE_IDX … macro
/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_12_0_offset.h769 #define mmPHYPLLF_PIXCLK_RESYNC_CNTL_BASE_IDX … macro