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Searched refs:mmOTG2_OTG_H_TIMING_CNTL_BASE_IDX (Results 1 – 6 of 6) sorted by relevance

/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_3_0_1_offset.h6931 #define mmOTG2_OTG_H_TIMING_CNTL_BASE_IDX … macro
Ddcn_1_0_offset.h6718 #define mmOTG2_OTG_H_TIMING_CNTL_BASE_IDX … macro
Ddcn_2_1_0_offset.h8372 #define mmOTG2_OTG_H_TIMING_CNTL_BASE_IDX … macro
Ddcn_3_0_2_offset.h8260 #define mmOTG2_OTG_H_TIMING_CNTL_BASE_IDX … macro
Ddcn_2_0_0_offset.h9403 #define mmOTG2_OTG_H_TIMING_CNTL_BASE_IDX … macro
Ddcn_3_0_0_offset.h9107 #define mmOTG2_OTG_H_TIMING_CNTL_BASE_IDX … macro