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Searched refs:mmOTG1_OTG_H_TIMING_CNTL_BASE_IDX (Results 1 – 8 of 8) sorted by relevance

/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_2_0_3_offset.h4918 #define mmOTG1_OTG_H_TIMING_CNTL_BASE_IDX … macro
Ddcn_3_0_3_offset.h4300 #define mmOTG1_OTG_H_TIMING_CNTL_BASE_IDX … macro
Ddcn_3_0_1_offset.h6713 #define mmOTG1_OTG_H_TIMING_CNTL_BASE_IDX … macro
Ddcn_1_0_offset.h6500 #define mmOTG1_OTG_H_TIMING_CNTL_BASE_IDX … macro
Ddcn_2_1_0_offset.h8158 #define mmOTG1_OTG_H_TIMING_CNTL_BASE_IDX … macro
Ddcn_3_0_2_offset.h8042 #define mmOTG1_OTG_H_TIMING_CNTL_BASE_IDX … macro
Ddcn_2_0_0_offset.h9189 #define mmOTG1_OTG_H_TIMING_CNTL_BASE_IDX … macro
Ddcn_3_0_0_offset.h8887 #define mmOTG1_OTG_H_TIMING_CNTL_BASE_IDX … macro