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Searched refs:mmMPCC0_MPCC_UPDATE_LOCK_SEL (Results 1 – 8 of 8) sorted by relevance

/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_2_0_3_offset.h3581 #define mmMPCC0_MPCC_UPDATE_LOCK_SEL … macro
Ddcn_3_0_3_offset.h6104 #define mmMPCC0_MPCC_UPDATE_LOCK_SEL … macro
Ddcn_3_0_1_offset.h10254 #define mmMPCC0_MPCC_UPDATE_LOCK_SEL … macro
Ddcn_1_0_offset.h5371 #define mmMPCC0_MPCC_UPDATE_LOCK_SEL … macro
Ddcn_2_1_0_offset.h5608 #define mmMPCC0_MPCC_UPDATE_LOCK_SEL … macro
Ddcn_3_0_2_offset.h12478 #define mmMPCC0_MPCC_UPDATE_LOCK_SEL … macro
Ddcn_2_0_0_offset.h6546 #define mmMPCC0_MPCC_UPDATE_LOCK_SEL … macro
Ddcn_3_0_0_offset.h13762 #define mmMPCC0_MPCC_UPDATE_LOCK_SEL … macro