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Searched refs:mmMC_VM_MX_L1_TLB_CNTL (Results 1 – 16 of 16) sorted by relevance

/linux-5.19.10/drivers/gpu/drm/amd/amdgpu/
Dgfxhub_v1_0.c157 tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL); in gfxhub_v1_0_init_tlb_regs()
169 WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp); in gfxhub_v1_0_init_tlb_regs()
355 tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL); in gfxhub_v1_0_gart_disable()
361 WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp); in gfxhub_v1_0_gart_disable()
Dmmhub_v1_0.c140 tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL); in mmhub_v1_0_init_tlb_regs()
152 WREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp); in mmhub_v1_0_init_tlb_regs()
351 tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL); in mmhub_v1_0_gart_disable()
357 WREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp); in mmhub_v1_0_gart_disable()
Dgmc_v7_0.c628 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); in gmc_v7_0_gart_enable()
634 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); in gmc_v7_0_gart_enable()
748 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); in gmc_v7_0_gart_disable()
752 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); in gmc_v7_0_gart_disable()
Dgmc_v8_0.c851 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); in gmc_v8_0_gart_enable()
857 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); in gmc_v8_0_gart_enable()
988 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); in gmc_v8_0_gart_disable()
992 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); in gmc_v8_0_gart_disable()
Dgmc_v6_0.c484 WREG32(mmMC_VM_MX_L1_TLB_CNTL, in gmc_v6_0_gart_enable()
595 WREG32(mmMC_VM_MX_L1_TLB_CNTL, in gmc_v6_0_gart_disable()
/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/gmc/
Dgmc_7_0_d.h257 #define mmMC_VM_MX_L1_TLB_CNTL 0x819 macro
Dgmc_8_2_d.h294 #define mmMC_VM_MX_L1_TLB_CNTL 0x819 macro
Dgmc_6_0_d.h1051 #define mmMC_VM_MX_L1_TLB_CNTL 0x0819 macro
Dgmc_7_1_d.h288 #define mmMC_VM_MX_L1_TLB_CNTL 0x819 macro
Dgmc_8_1_d.h297 #define mmMC_VM_MX_L1_TLB_CNTL 0x819 macro
/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/mmhub/
Dmmhub_1_0_offset.h1946 #define mmMC_VM_MX_L1_TLB_CNTL macro
Dmmhub_9_1_offset.h1978 #define mmMC_VM_MX_L1_TLB_CNTL macro
Dmmhub_9_3_0_offset.h1970 #define mmMC_VM_MX_L1_TLB_CNTL macro
/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h1698 #define mmMC_VM_MX_L1_TLB_CNTL macro
Dgc_9_1_offset.h1717 #define mmMC_VM_MX_L1_TLB_CNTL macro
Dgc_9_2_1_offset.h1659 #define mmMC_VM_MX_L1_TLB_CNTL macro