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Searched refs:mmMC_SEQ_WR_CTL_D0 (Results 1 – 6 of 6) sorted by relevance

/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/gmc/
Dgmc_6_0_d.h1003 #define mmMC_SEQ_WR_CTL_D0 0x0A2F macro
Dgmc_7_1_d.h643 #define mmMC_SEQ_WR_CTL_D0 0xa2f macro
Dgmc_8_1_d.h747 #define mmMC_SEQ_WR_CTL_D0 0xa2f macro
/linux-5.19.10/drivers/gpu/drm/amd/pm/powerplay/smumgr/
Diceland_smumgr.c2427 case mmMC_SEQ_WR_CTL_D0: in iceland_check_s0_mc_reg_index()
2629 …gister(hwmgr->device, mmMC_SEQ_WR_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0)); in iceland_initialize_mc_reg_table()
Dci_smumgr.c2501 case mmMC_SEQ_WR_CTL_D0: in ci_check_s0_mc_reg_index()
2703 …gister(hwmgr->device, mmMC_SEQ_WR_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0)); in ci_initialize_mc_reg_table()
Dtonga_smumgr.c2890 case mmMC_SEQ_WR_CTL_D0: in tonga_check_s0_mc_reg_index()
3108 cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0)); in tonga_initialize_mc_reg_table()