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Searched refs:mmMAILBOX_CONTROL (Results 1 – 6 of 6) sorted by relevance

/linux-5.19.10/drivers/gpu/drm/amd/amdgpu/
Dmxgpu_vi.c325 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_mailbox_send_ack()
327 WREG32_NO_KIQ(mmMAILBOX_CONTROL, reg); in xgpu_vi_mailbox_send_ack()
330 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_mailbox_send_ack()
339 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_mailbox_send_ack()
347 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_mailbox_set_valid()
350 WREG32_NO_KIQ(mmMAILBOX_CONTROL, reg); in xgpu_vi_mailbox_set_valid()
374 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_mailbox_rcv_msg()
395 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_poll_ack()
405 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_poll_ack()
Dmxgpu_nv.h64 #define mmMAILBOX_CONTROL 0xE5E macro
66 #define NV_MAIBOX_CONTROL_TRN_OFFSET_BYTE (mmMAILBOX_CONTROL * 4)
/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/bif/
Dbif_5_0_d.h186 #define mmMAILBOX_CONTROL 0x14d0 macro
/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/nbif/
Dnbif_6_1_offset.h1149 #define mmMAILBOX_CONTROL … macro
/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/nbio/
Dnbio_7_0_offset.h4502 #define mmMAILBOX_CONTROL … macro
Dnbio_7_4_offset.h2932 #define mmMAILBOX_CONTROL … macro