Searched refs:mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR (Results 1 – 4 of 4) sorted by relevance
120 #define mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR 0x800040 macro
294 #define mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR 0x800040 macro
1122 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); in goya_init_dma_qman()1124 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); in goya_init_dma_qman()1165 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); in goya_init_dma_ch()1167 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); in goya_init_dma_ch()1391 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR, in goya_init_cpu_queues()1863 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); in goya_init_mme_qman()1865 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); in goya_init_mme_qman()1912 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); in goya_init_mme_cmdq()1914 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); in goya_init_mme_cmdq()1970 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); in goya_init_tpc_qman()[all …]
2791 mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR : in gaudi_init_pci_dma_qman()2846 mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR : in gaudi_init_dma_core()2962 mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR : in gaudi_init_hbm_dma_qman()3095 mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR : in gaudi_init_mme_qman()3231 mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR : in gaudi_init_tpc_qman()3388 mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR : in gaudi_init_nic_qman()4042 mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR : in gaudi_init_cpu_queues()4233 mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR : in gaudi_hw_fini()4703 mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR : in gaudi_ring_doorbell()8898 mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR : in gaudi_enable_events_from_fw()