Searched refs:mmGDS_VMID0_BASE (Results 1 – 13 of 13) sorted by relevance
| /linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/gca/ |
| D | gfx_7_0_d.h | 2217 #define mmGDS_VMID0_BASE 0x3300 macro
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| D | gfx_7_2_d.h | 2239 #define mmGDS_VMID0_BASE 0x3300 macro
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| D | gfx_8_0_d.h | 2437 #define mmGDS_VMID0_BASE 0x3300 macro
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| D | gfx_8_1_d.h | 2416 #define mmGDS_VMID0_BASE 0x3300 macro
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| /linux-5.19.10/drivers/gpu/drm/amd/amdgpu/ |
| D | gfx_v9_0.c | 2540 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0); in gfx_v9_0_init_compute_vmid()
2558 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0); in gfx_v9_0_init_gds_vmid()
4232 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid, in gfx_v9_0_ring_emit_gds_switch()
4503 WREG32_SOC15(GC, 0, mmGDS_VMID0_BASE, 0x00000000); in gfx_v9_0_do_edc_gds_workarounds()
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| D | gfx_v10_0.c | 5117 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0); in gfx_v10_0_init_compute_vmid()
5135 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0); in gfx_v10_0_init_gds_vmid()
7737 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid, in gfx_v10_0_ring_emit_gds_switch()
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| D | gfx_v7_0.c | 95 {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
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| D | gfx_v8_0.c | 179 {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
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| /linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| D | gc_9_0_offset.h | 3043 #define mmGDS_VMID0_BASE … macro
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| D | gc_9_1_offset.h | 3273 #define mmGDS_VMID0_BASE … macro
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| D | gc_9_2_1_offset.h | 3223 #define mmGDS_VMID0_BASE … macro
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| D | gc_10_1_0_offset.h | 5523 #define mmGDS_VMID0_BASE … macro
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| D | gc_10_3_0_offset.h | 5150 #define mmGDS_VMID0_BASE … macro
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