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Searched refs:mmDSCC4_DSCC_MEM_POWER_CONTROL_BASE_IDX (Results 1 – 4 of 4) sorted by relevance

/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_2_1_0_offset.h12088 #define mmDSCC4_DSCC_MEM_POWER_CONTROL_BASE_IDX … macro
Ddcn_3_0_2_offset.h12161 #define mmDSCC4_DSCC_MEM_POWER_CONTROL_BASE_IDX … macro
Ddcn_2_0_0_offset.h14219 #define mmDSCC4_DSCC_MEM_POWER_CONTROL_BASE_IDX … macro
Ddcn_3_0_0_offset.h13316 #define mmDSCC4_DSCC_MEM_POWER_CONTROL_BASE_IDX … macro