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Searched refs:mmDP5_DP_SEC_CNTL1_BASE_IDX (Results 1 – 5 of 5) sorted by relevance

/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_1_0_offset.h9960 #define mmDP5_DP_SEC_CNTL1_BASE_IDX … macro
Ddcn_3_0_2_offset.h11302 #define mmDP5_DP_SEC_CNTL1_BASE_IDX … macro
Ddcn_2_0_0_offset.h12647 #define mmDP5_DP_SEC_CNTL1_BASE_IDX … macro
Ddcn_3_0_0_offset.h12445 #define mmDP5_DP_SEC_CNTL1_BASE_IDX … macro
/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_12_0_offset.h11681 #define mmDP5_DP_SEC_CNTL1_BASE_IDX … macro