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Searched refs:mmDP0_DP_SEC_CNTL1 (Results 1 – 14 of 14) sorted by relevance

/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_6_0_d.h3151 #define mmDP0_DP_SEC_CNTL1 0x1CAB macro
Ddce_8_0_d.h4012 #define mmDP0_DP_SEC_CNTL1 0x1cab macro
Ddce_10_0_d.h4644 #define mmDP0_DP_SEC_CNTL1 0x4ac4 macro
Ddce_11_0_d.h4677 #define mmDP0_DP_SEC_CNTL1 0x4ac4 macro
Ddce_11_2_d.h5909 #define mmDP0_DP_SEC_CNTL1 0x4ac4 macro
Ddce_12_0_offset.h10260 #define mmDP0_DP_SEC_CNTL1 … macro
/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_2_0_3_offset.h5524 #define mmDP0_DP_SEC_CNTL1 … macro
Ddcn_3_0_3_offset.h5010 #define mmDP0_DP_SEC_CNTL1 … macro
Ddcn_3_0_1_offset.h7980 #define mmDP0_DP_SEC_CNTL1 … macro
Ddcn_1_0_offset.h8409 #define mmDP0_DP_SEC_CNTL1 … macro
Ddcn_2_1_0_offset.h9913 #define mmDP0_DP_SEC_CNTL1 … macro
Ddcn_3_0_2_offset.h9592 #define mmDP0_DP_SEC_CNTL1 … macro
Ddcn_2_0_0_offset.h11006 #define mmDP0_DP_SEC_CNTL1 … macro
Ddcn_3_0_0_offset.h10727 #define mmDP0_DP_SEC_CNTL1 … macro