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Searched refs:mmDMU_MEM_PWR_CNTL_BASE_IDX (Results 1 – 7 of 7) sorted by relevance

/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_3_0_3_offset.h304 #define mmDMU_MEM_PWR_CNTL_BASE_IDX … macro
Ddcn_3_0_1_offset.h503 #define mmDMU_MEM_PWR_CNTL_BASE_IDX … macro
Ddcn_1_0_offset.h931 #define mmDMU_MEM_PWR_CNTL_BASE_IDX … macro
Ddcn_2_1_0_offset.h559 #define mmDMU_MEM_PWR_CNTL_BASE_IDX … macro
Ddcn_3_0_2_offset.h471 #define mmDMU_MEM_PWR_CNTL_BASE_IDX … macro
Ddcn_2_0_0_offset.h597 #define mmDMU_MEM_PWR_CNTL_BASE_IDX … macro
Ddcn_3_0_0_offset.h482 #define mmDMU_MEM_PWR_CNTL_BASE_IDX … macro