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Searched refs:mmDC_GPU_TIMER_READ_BASE_IDX (Results 1 – 8 of 8) sorted by relevance

/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_3_0_3_offset.h456 #define mmDC_GPU_TIMER_READ_BASE_IDX … macro
Ddcn_3_0_1_offset.h655 #define mmDC_GPU_TIMER_READ_BASE_IDX … macro
Ddcn_1_0_offset.h1075 #define mmDC_GPU_TIMER_READ_BASE_IDX … macro
Ddcn_2_1_0_offset.h711 #define mmDC_GPU_TIMER_READ_BASE_IDX … macro
Ddcn_3_0_2_offset.h629 #define mmDC_GPU_TIMER_READ_BASE_IDX … macro
Ddcn_2_0_0_offset.h749 #define mmDC_GPU_TIMER_READ_BASE_IDX … macro
Ddcn_3_0_0_offset.h642 #define mmDC_GPU_TIMER_READ_BASE_IDX … macro
/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_12_0_offset.h1883 #define mmDC_GPU_TIMER_READ_BASE_IDX … macro