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Searched refs:mmDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX (Results 1 – 8 of 8) sorted by relevance

/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_2_0_3_offset.h137 #define mmDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX … macro
Ddcn_3_0_3_offset.h224 #define mmDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX … macro
Ddcn_3_0_1_offset.h337 #define mmDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX … macro
Ddcn_1_0_offset.h655 #define mmDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX … macro
Ddcn_2_1_0_offset.h293 #define mmDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX … macro
Ddcn_3_0_2_offset.h287 #define mmDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX … macro
Ddcn_2_0_0_offset.h303 #define mmDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX … macro
Ddcn_3_0_0_offset.h284 #define mmDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX … macro