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Searched refs:mmDCCG_AUDIO_DTO0_PHASE (Results 1 – 18 of 18) sorted by relevance

/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_6_0_d.h1135 #define mmDCCG_AUDIO_DTO0_PHASE 0x016C macro
Ddce_8_0_d.h1077 #define mmDCCG_AUDIO_DTO0_PHASE 0x16c macro
Ddce_10_0_d.h1226 #define mmDCCG_AUDIO_DTO0_PHASE 0x16c macro
Ddce_11_0_d.h1037 #define mmDCCG_AUDIO_DTO0_PHASE 0x16c macro
Ddce_11_2_d.h1115 #define mmDCCG_AUDIO_DTO0_PHASE 0x16c macro
Ddce_12_0_offset.h842 #define mmDCCG_AUDIO_DTO0_PHASE … macro
/linux-5.19.10/drivers/gpu/drm/amd/amdgpu/
Ddce_v6_0.c1514 WREG32(mmDCCG_AUDIO_DTO0_PHASE, 24000); in dce_v6_0_audio_set_dto()
Ddce_v8_0.c1509 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase); in dce_v8_0_audio_set_dto()
Ddce_v10_0.c1562 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase); in dce_v10_0_audio_set_dto()
Ddce_v11_0.c1604 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase); in dce_v11_0_audio_set_dto()
/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_2_0_3_offset.h126 #define mmDCCG_AUDIO_DTO0_PHASE … macro
Ddcn_3_0_3_offset.h213 #define mmDCCG_AUDIO_DTO0_PHASE … macro
Ddcn_3_0_1_offset.h326 #define mmDCCG_AUDIO_DTO0_PHASE … macro
Ddcn_1_0_offset.h644 #define mmDCCG_AUDIO_DTO0_PHASE … macro
Ddcn_2_1_0_offset.h282 #define mmDCCG_AUDIO_DTO0_PHASE … macro
Ddcn_3_0_2_offset.h276 #define mmDCCG_AUDIO_DTO0_PHASE … macro
Ddcn_2_0_0_offset.h292 #define mmDCCG_AUDIO_DTO0_PHASE … macro
Ddcn_3_0_0_offset.h273 #define mmDCCG_AUDIO_DTO0_PHASE … macro