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Searched refs:mmCP_MQD_BASE_ADDR_HI (Results 1 – 13 of 13) sorted by relevance

/linux-5.19.10/drivers/gpu/drm/amd/pm/powerplay/inc/
Dpolaris10_pwrvirus.h1506 { 0x000000b4, mmCP_MQD_BASE_ADDR_HI },
1516 { 0x000000b4, mmCP_MQD_BASE_ADDR_HI },
1526 { 0x000000b4, mmCP_MQD_BASE_ADDR_HI },
1536 { 0x000000b4, mmCP_MQD_BASE_ADDR_HI },
/linux-5.19.10/drivers/gpu/drm/amd/amdgpu/
Dmes_v10_1.c795 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
Dgfx_v10_0.c6683 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); in gfx_v10_0_gfx_queue_init_register()
6994 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, in gfx_v10_0_kiq_init_register()
Dgfx_v9_0.c3611 WREG32_SOC15_RLC(GC, 0, mmCP_MQD_BASE_ADDR_HI, in gfx_v9_0_kiq_init_register()
/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_7_0_d.h568 #define mmCP_MQD_BASE_ADDR_HI 0x3246 macro
Dgfx_7_2_d.h581 #define mmCP_MQD_BASE_ADDR_HI 0x3246 macro
Dgfx_8_0_d.h631 #define mmCP_MQD_BASE_ADDR_HI 0x3246 macro
Dgfx_8_1_d.h631 #define mmCP_MQD_BASE_ADDR_HI 0x3246 macro
/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h2821 #define mmCP_MQD_BASE_ADDR_HI macro
Dgc_9_1_offset.h3049 #define mmCP_MQD_BASE_ADDR_HI macro
Dgc_9_2_1_offset.h3005 #define mmCP_MQD_BASE_ADDR_HI macro
Dgc_10_1_0_offset.h5285 #define mmCP_MQD_BASE_ADDR_HI macro
Dgc_10_3_0_offset.h4920 #define mmCP_MQD_BASE_ADDR_HI macro