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Searched refs:mmCNVC_CFG0_PRE_CSC_B_C11_C12_BASE_IDX (Results 1 – 4 of 4) sorted by relevance

/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_3_0_3_offset.h2512 #define mmCNVC_CFG0_PRE_CSC_B_C11_C12_BASE_IDX … macro
Ddcn_3_0_1_offset.h3323 #define mmCNVC_CFG0_PRE_CSC_B_C11_C12_BASE_IDX … macro
Ddcn_3_0_2_offset.h3868 #define mmCNVC_CFG0_PRE_CSC_B_C11_C12_BASE_IDX … macro
Ddcn_3_0_0_offset.h3914 #define mmCNVC_CFG0_PRE_CSC_B_C11_C12_BASE_IDX … macro