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Searched refs:mmCGTS_CU2_TA_SQC_CTRL_REG_BASE_IDX (Results 1 – 3 of 3) sorted by relevance

/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h6338 #define mmCGTS_CU2_TA_SQC_CTRL_REG_BASE_IDX … macro
Dgc_9_1_offset.h6560 #define mmCGTS_CU2_TA_SQC_CTRL_REG_BASE_IDX … macro
Dgc_9_2_1_offset.h6572 #define mmCGTS_CU2_TA_SQC_CTRL_REG_BASE_IDX … macro