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Searched refs:mem_level (Results 1 – 3 of 3) sorted by relevance

/linux-5.19.10/drivers/gpu/drm/amd/pm/powerplay/smumgr/
Dvegam_smumgr.c965 uint32_t clock, struct SMU75_Discrete_MemoryLevel *mem_level) in vegam_calculate_mclk_params() argument
974 mem_level->MclkFrequency = (uint32_t)mpll_param.ulClock; in vegam_calculate_mclk_params()
975 mem_level->Fcw_int = (uint16_t)mpll_param.ulMclk_fcw_int; in vegam_calculate_mclk_params()
976 mem_level->Fcw_frac = (uint16_t)mpll_param.ulMclk_fcw_frac; in vegam_calculate_mclk_params()
977 mem_level->Postdiv = (uint8_t)mpll_param.ulPostDiv; in vegam_calculate_mclk_params()
983 uint32_t clock, struct SMU75_Discrete_MemoryLevel *mem_level) in vegam_populate_single_memory_level() argument
995 &mem_level->MinVoltage, &mem_level->MinMvdd); in vegam_populate_single_memory_level()
1001 result = vegam_calculate_mclk_params(hwmgr, clock, mem_level); in vegam_populate_single_memory_level()
1006 mem_level->EnabledForThrottle = 1; in vegam_populate_single_memory_level()
1007 mem_level->EnabledForActivity = 0; in vegam_populate_single_memory_level()
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Dfiji_smumgr.c1162 uint32_t clock, struct SMU73_Discrete_MemoryLevel *mem_level) in fiji_populate_single_memory_level() argument
1179 (uint32_t *)(&mem_level->MinVoltage), &mem_level->MinMvdd); in fiji_populate_single_memory_level()
1185 mem_level->EnabledForThrottle = 1; in fiji_populate_single_memory_level()
1186 mem_level->EnabledForActivity = 0; in fiji_populate_single_memory_level()
1187 mem_level->UpHyst = data->current_profile_setting.mclk_up_hyst; in fiji_populate_single_memory_level()
1188 mem_level->DownHyst = data->current_profile_setting.mclk_down_hyst; in fiji_populate_single_memory_level()
1189 mem_level->VoltageDownHyst = 0; in fiji_populate_single_memory_level()
1190 mem_level->ActivityLevel = data->current_profile_setting.mclk_activity; in fiji_populate_single_memory_level()
1191 mem_level->StutterEnable = false; in fiji_populate_single_memory_level()
1193 mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; in fiji_populate_single_memory_level()
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Dpolaris10_smumgr.c1154 uint32_t clock, struct SMU74_Discrete_MemoryLevel *mem_level) in polaris10_populate_single_memory_level() argument
1172 &mem_level->MinVoltage, &mem_level->MinMvdd); in polaris10_populate_single_memory_level()
1178 mem_level->MclkFrequency = clock; in polaris10_populate_single_memory_level()
1179 mem_level->EnabledForThrottle = 1; in polaris10_populate_single_memory_level()
1180 mem_level->EnabledForActivity = 0; in polaris10_populate_single_memory_level()
1181 mem_level->UpHyst = data->current_profile_setting.mclk_up_hyst; in polaris10_populate_single_memory_level()
1182 mem_level->DownHyst = data->current_profile_setting.mclk_down_hyst; in polaris10_populate_single_memory_level()
1183 mem_level->VoltageDownHyst = 0; in polaris10_populate_single_memory_level()
1184 mem_level->ActivityLevel = data->current_profile_setting.mclk_activity; in polaris10_populate_single_memory_level()
1185 mem_level->StutterEnable = false; in polaris10_populate_single_memory_level()
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