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Searched refs:mdiv (Results 1 – 25 of 34) sorted by relevance

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/linux-5.19.10/drivers/clk/bcm/
Dclk-ns2.c62 .mdiv = REG_VAL(0x18, 0, 8),
68 .mdiv = REG_VAL(0x18, 8, 8),
74 .mdiv = REG_VAL(0x14, 0, 8),
80 .mdiv = REG_VAL(0x14, 8, 8),
86 .mdiv = REG_VAL(0x14, 16, 8),
92 .mdiv = REG_VAL(0x14, 24, 8),
124 .mdiv = REG_VAL(0x18, 0, 8),
130 .mdiv = REG_VAL(0x18, 8, 8),
136 .mdiv = REG_VAL(0x14, 0, 8),
142 .mdiv = REG_VAL(0x14, 8, 8),
[all …]
Dclk-sr.c52 .mdiv = REG_VAL(0x18, 0, 9),
58 .mdiv = REG_VAL(0x18, 10, 9),
64 .mdiv = REG_VAL(0x18, 20, 9),
70 .mdiv = REG_VAL(0x1c, 0, 9),
76 .mdiv = REG_VAL(0x1c, 10, 9),
82 .mdiv = REG_VAL(0x1c, 20, 9),
112 .mdiv = REG_VAL(0x18, 0, 9),
118 .mdiv = REG_VAL(0x18, 10, 9),
124 .mdiv = REG_VAL(0x18, 20, 9),
130 .mdiv = REG_VAL(0x1c, 0, 9),
[all …]
Dclk-cygnus.c76 .mdiv = REG_VAL(0x20, 0, 8),
82 .mdiv = REG_VAL(0x20, 10, 8),
88 .mdiv = REG_VAL(0x20, 20, 8),
94 .mdiv = REG_VAL(0x24, 0, 8),
100 .mdiv = REG_VAL(0x24, 10, 8),
106 .mdiv = REG_VAL(0x24, 20, 8),
134 .mdiv = REG_VAL(0x8, 0, 8),
140 .mdiv = REG_VAL(0x8, 10, 8),
146 .mdiv = REG_VAL(0x8, 20, 8),
152 .mdiv = REG_VAL(0xc, 0, 8),
[all …]
Dclk-iproc-armpll.c119 int mdiv; in __get_mdiv() local
127 mdiv = 1; in __get_mdiv()
132 mdiv = val & IPROC_CLK_PLLARMC_MDIV_MASK; in __get_mdiv()
133 if (mdiv == 0) in __get_mdiv()
134 mdiv = 256; in __get_mdiv()
139 mdiv = val & IPROC_CLK_PLLARMCTL5_H_MDIV_MASK; in __get_mdiv()
140 if (mdiv == 0) in __get_mdiv()
141 mdiv = 256; in __get_mdiv()
145 mdiv = -EFAULT; in __get_mdiv()
148 return mdiv; in __get_mdiv()
[all …]
Dclk-nsp.c61 .mdiv = REG_VAL(0x18, 16, 8),
67 .mdiv = REG_VAL(0x18, 8, 8),
73 .mdiv = REG_VAL(0x18, 0, 8),
79 .mdiv = REG_VAL(0x1c, 16, 8),
85 .mdiv = REG_VAL(0x1c, 8, 8),
91 .mdiv = REG_VAL(0x1c, 0, 8),
118 .mdiv = REG_VAL(0x8, 24, 8),
124 .mdiv = REG_VAL(0x8, 16, 8),
130 .mdiv = REG_VAL(0x8, 8, 8),
Dclk-iproc-pll.c627 unsigned int mdiv; in iproc_clk_recalc_rate() local
633 val = readl(pll->control_base + ctrl->mdiv.offset); in iproc_clk_recalc_rate()
634 mdiv = (val >> ctrl->mdiv.shift) & bit_mask(ctrl->mdiv.width); in iproc_clk_recalc_rate()
635 if (mdiv == 0) in iproc_clk_recalc_rate()
636 mdiv = 256; in iproc_clk_recalc_rate()
639 rate = parent_rate / (mdiv * 2); in iproc_clk_recalc_rate()
641 rate = parent_rate / mdiv; in iproc_clk_recalc_rate()
687 val = readl(pll->control_base + ctrl->mdiv.offset); in iproc_clk_set_rate()
689 val &= ~(bit_mask(ctrl->mdiv.width) << ctrl->mdiv.shift); in iproc_clk_set_rate()
691 val &= ~(bit_mask(ctrl->mdiv.width) << ctrl->mdiv.shift); in iproc_clk_set_rate()
[all …]
Dclk-iproc.h197 struct iproc_clk_reg_op mdiv; member
/linux-5.19.10/drivers/clk/samsung/
Dclk-pll.c153 u32 pll_con, mdiv, pdiv, sdiv; in samsung_pll2126_recalc_rate() local
157 mdiv = (pll_con >> PLL2126_MDIV_SHIFT) & PLL2126_MDIV_MASK; in samsung_pll2126_recalc_rate()
161 fvco *= (mdiv + 8); in samsung_pll2126_recalc_rate()
186 u32 pll_con, mdiv, pdiv, sdiv; in samsung_pll3000_recalc_rate() local
190 mdiv = (pll_con >> PLL3000_MDIV_SHIFT) & PLL3000_MDIV_MASK; in samsung_pll3000_recalc_rate()
194 fvco *= (2 * (mdiv + 8)); in samsung_pll3000_recalc_rate()
223 u32 mdiv, pdiv, sdiv, pll_con; in samsung_pll35xx_recalc_rate() local
227 mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK; in samsung_pll35xx_recalc_rate()
231 fvco *= mdiv; in samsung_pll35xx_recalc_rate()
245 return (rate->mdiv != old_mdiv || rate->pdiv != old_pdiv); in samsung_pll35xx_mp_change()
[all …]
Dclk-pll.h54 .mdiv = (_m), \
63 .mdiv = (_m), \
72 .mdiv = (_m), \
81 .mdiv = (_m), \
91 .mdiv = (_m), \
101 .mdiv = (_m), \
112 .mdiv = (_m), \
126 unsigned int mdiv; member
/linux-5.19.10/drivers/clk/imx/
Dclk-pll14xx.c104 static long pll14xx_calc_rate(struct clk_pll14xx *pll, int mdiv, int pdiv, in pll14xx_calc_rate() argument
110 fvco *= (mdiv * 65536 + kdiv); in pll14xx_calc_rate()
118 static long pll1443x_calc_kdiv(int mdiv, int pdiv, int sdiv, in pll1443x_calc_kdiv() argument
124 kdiv = ((rate * ((pdiv * 65536) << sdiv) + prate / 2) / prate) - (mdiv * 65536); in pll1443x_calc_kdiv()
133 int mdiv, pdiv, sdiv, kdiv; in imx_pll14xx_calc_settings() local
155 t->mdiv = tt->mdiv; in imx_pll14xx_calc_settings()
163 mdiv = FIELD_GET(MDIV_MASK, pll_div_ctl0); in imx_pll14xx_calc_settings()
169 rate_min = pll14xx_calc_rate(pll, mdiv, pdiv, sdiv, KDIV_MIN, prate); in imx_pll14xx_calc_settings()
170 rate_max = pll14xx_calc_rate(pll, mdiv, pdiv, sdiv, KDIV_MAX, prate); in imx_pll14xx_calc_settings()
173 kdiv = pll1443x_calc_kdiv(mdiv, pdiv, sdiv, rate, prate); in imx_pll14xx_calc_settings()
[all …]
Dclk.h60 unsigned int mdiv; member
262 .mdiv = (_m), \
270 .mdiv = (_m), \
/linux-5.19.10/arch/arm/mach-s3c/
Dregs-s3c2443-clock.h153 unsigned int mdiv, pdiv, sdiv; in s3c2443_get_mpll() local
156 mdiv = pllval >> S3C2443_PLLCON_MDIVSHIFT; in s3c2443_get_mpll()
160 mdiv &= S3C2443_PLLCON_MDIVMASK; in s3c2443_get_mpll()
164 fvco = (uint64_t)baseclk * (2 * (mdiv + 8)); in s3c2443_get_mpll()
173 unsigned int mdiv, pdiv, sdiv; in s3c2443_get_epll() local
176 mdiv = pllval >> S3C2443_PLLCON_MDIVSHIFT; in s3c2443_get_epll()
180 mdiv &= S3C2443_PLLCON_MDIVMASK; in s3c2443_get_epll()
184 fvco = (uint64_t)baseclk * (mdiv + 8); in s3c2443_get_epll()
/linux-5.19.10/drivers/clk/st/
Dclkgen-fsyn.c35 unsigned long mdiv; member
58 struct clkgen_field mdiv[QUADFS_MAX_CHAN]; member
102 .mdiv = { CLKGEN_FIELD(0x304, 0x1f, 15),
165 .mdiv = { CLKGEN_FIELD(0x2b4, 0x1f, 15),
554 CLKGEN_WRITE(fs, mdiv[fs->chan], fs->md); in quadfs_fsynth_program_rate()
639 res = (P20 * (32 + fs->mdiv) + 32 * fs->pe) * s * ns; in clk_fs660c32_dig_get_rate()
663 fs_tmp.mdiv = (unsigned long) m; in clk_fs660c32_get_pe()
673 fs->mdiv = m; in clk_fs660c32_get_pe()
719 fs_tmp.mdiv = fs->mdiv; in clk_fs660c32_dig_get_params()
752 params->mdiv = CLKGEN_READ(fs, mdiv[fs->chan]); in quadfs_fsynt_get_hw_value_for_recalc()
[all …]
/linux-5.19.10/drivers/clk/socfpga/
Dclk-pll-s10.c65 unsigned long arefdiv, reg, mdiv; in agilex_clk_pll_recalc_rate() local
76 mdiv = reg & SOCFPGA_AGILEX_PLL_MDIV_MASK; in agilex_clk_pll_recalc_rate()
78 vco_freq = (unsigned long long)vco_freq * mdiv; in agilex_clk_pll_recalc_rate()
86 unsigned long mdiv; in clk_pll_recalc_rate() local
100 mdiv = (reg & SOCFPGA_PLL_MDIV_MASK) >> SOCFPGA_PLL_MDIV_SHIFT; in clk_pll_recalc_rate()
101 vco_freq = (unsigned long long)vco_freq * (mdiv + 6); in clk_pll_recalc_rate()
/linux-5.19.10/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
Dgk104.c35 u32 mdiv; member
320 info->mdiv |= 0x80000000; in calc_clk()
321 info->mdiv |= div1D; in calc_clk()
327 info->mdiv |= 0x80000000; in calc_clk()
328 info->mdiv |= div1P << 8; in calc_clk()
416 nvkm_mask(device, 0x137250 + (idx * 0x04), 0x00003f00, info->mdiv); in gk104_clk_prog_3()
418 nvkm_mask(device, 0x137250 + (idx * 0x04), 0x0000003f, info->mdiv); in gk104_clk_prog_3()
Dgf100.c35 u32 mdiv; member
307 info->mdiv |= 0x80000000; in calc_clk()
308 info->mdiv |= div1D; in calc_clk()
314 info->mdiv |= 0x80000000; in calc_clk()
315 info->mdiv |= div1P << 8; in calc_clk()
412 nvkm_mask(device, 0x137250 + (idx * 0x04), 0x00003f3f, info->mdiv); in gf100_clk_prog_4()
/linux-5.19.10/sound/soc/codecs/
Dak4375.c279 unsigned int mclk, plm, mdiv, div; in ak4375_dai_set_pll() local
327 mdiv = freq_out / mclk - 1; in ak4375_dai_set_pll()
332 mdiv = freq_out / mclk - 1; in ak4375_dai_set_pll()
337 mdiv = 4; in ak4375_dai_set_pll()
359 snd_soc_component_write(component, AK4375_14_DAC_CLK_DIVIDER, mdiv); in ak4375_dai_set_pll()
362 ak4375->rate, mclk, freq_in, freq_out, ak4375->pld, plm, mdiv, div); in ak4375_dai_set_pll()
/linux-5.19.10/drivers/media/dvb-frontends/
Dhorus3a.c172 u8 mdiv = 0; in horus3a_set_params() local
190 mdiv = 1; in horus3a_set_params()
193 mdiv = 0; in horus3a_set_params()
296 data[4] = (u8)(mdiv << 7); in horus3a_set_params()
/linux-5.19.10/drivers/iio/frequency/
Dadf4350.c141 u16 mdiv, r_cnt = 0; in adf4350_set_freq() local
149 mdiv = 75; in adf4350_set_freq()
152 mdiv = 23; in adf4350_set_freq()
188 } while (mdiv > st->r0_int); in adf4350_set_freq()
/linux-5.19.10/drivers/gpu/drm/nouveau/nvkm/engine/device/
Dctrl.c126 args->v0.min = lo / domain->mdiv; in nvkm_control_mthd_pstate_attr()
127 args->v0.max = hi / domain->mdiv; in nvkm_control_mthd_pstate_attr()
/linux-5.19.10/drivers/gpu/drm/nouveau/include/nvkm/subdev/
Dclk.h80 int mdiv; member
/linux-5.19.10/drivers/clk/nxp/
Dclk-lpc18xx-cgu.c354 u32 ctrl, mdiv, msel, npdiv; in lpc18xx_pll0_recalc_rate() local
357 mdiv = readl(pll->reg + LPC18XX_CGU_PLL0USB_MDIV); in lpc18xx_pll0_recalc_rate()
368 msel = lpc18xx_pll0_mdec2msel(mdiv & LPC18XX_PLL0_MDIV_MDEC_MASK); in lpc18xx_pll0_recalc_rate()
/linux-5.19.10/drivers/i2c/busses/
Di2c-octeon-core.c661 int thp = 0x18, mdiv = 2, ndiv = 0, delta_hz = 1000000; in octeon_i2c_set_clock() local
689 mdiv = mdiv_idx; in octeon_i2c_set_clock()
696 octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CLKCTL, (mdiv << 3) | ndiv); in octeon_i2c_set_clock()
/linux-5.19.10/drivers/gpu/drm/i915/display/
Dintel_dpll.c1589 u32 mdiv; in vlv_prepare_pll() local
1619 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); in vlv_prepare_pll()
1620 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); in vlv_prepare_pll()
1621 mdiv |= ((bestn << DPIO_N_SHIFT)); in vlv_prepare_pll()
1622 mdiv |= (1 << DPIO_K_SHIFT); in vlv_prepare_pll()
1629 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); in vlv_prepare_pll()
1630 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); in vlv_prepare_pll()
1632 mdiv |= DPIO_ENABLE_CALIBRATION; in vlv_prepare_pll()
1633 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); in vlv_prepare_pll()
/linux-5.19.10/drivers/cpufreq/
Dtegra194-cpufreq.c204 return nltbl->ref_clk_hz / KHZ * ndiv / (nltbl->pdiv * nltbl->mdiv); in map_ndiv_to_freq()
479 freq_table_step_size = resp.mdiv * in init_freq_table()

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