| /linux-5.19.10/drivers/gpu/drm/amd/pm/swsmu/smu12/ |
| D | renoir_ppt.c | 244 uint32_t *mclk_mask, in renoir_get_profiling_clk_mask() argument
252 if (mclk_mask) in renoir_get_profiling_clk_mask()
254 *mclk_mask = NUM_MEMCLK_DPM_LEVELS - 1; in renoir_get_profiling_clk_mask()
260 if(mclk_mask) in renoir_get_profiling_clk_mask()
262 *mclk_mask = 0; in renoir_get_profiling_clk_mask()
277 uint32_t mclk_mask, soc_mask; in renoir_get_dpm_ultimate_freq() local
311 &mclk_mask, in renoir_get_dpm_ultimate_freq()
328 ret = renoir_get_dpm_clk_limited(smu, clk_type, mclk_mask, max); in renoir_get_dpm_ultimate_freq()
925 uint32_t sclk_mask, mclk_mask, soc_mask; in renoir_set_performance_level() local
1007 &mclk_mask, in renoir_set_performance_level()
[all …]
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| /linux-5.19.10/drivers/gpu/drm/amd/pm/swsmu/smu11/ |
| D | vangogh_ppt.c | 813 uint32_t *mclk_mask, in vangogh_get_profiling_clk_mask() argument
820 if (mclk_mask) in vangogh_get_profiling_clk_mask()
821 *mclk_mask = clk_table->NumDfPstatesEnabled - 1; in vangogh_get_profiling_clk_mask()
829 if (mclk_mask) in vangogh_get_profiling_clk_mask()
830 *mclk_mask = 0; in vangogh_get_profiling_clk_mask()
844 if (mclk_mask) in vangogh_get_profiling_clk_mask()
845 *mclk_mask = 0; in vangogh_get_profiling_clk_mask()
904 uint32_t mclk_mask; in vangogh_get_dpm_ultimate_freq() local
948 &mclk_mask, in vangogh_get_dpm_ultimate_freq()
957 ret = vangogh_get_dpm_clk_limited(smu, clk_type, mclk_mask, max); in vangogh_get_dpm_ultimate_freq()
[all …]
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| /linux-5.19.10/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| D | vega12_hwmgr.c | 1697 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) in vega12_get_profiling_clk_mask() argument
1705 *mclk_mask = 0; in vega12_get_profiling_clk_mask()
1712 *mclk_mask = VEGA12_UMD_PSTATE_MCLK_LEVEL; in vega12_get_profiling_clk_mask()
1719 *mclk_mask = 0; in vega12_get_profiling_clk_mask()
1722 *mclk_mask = mem_dpm_table->count - 1; in vega12_get_profiling_clk_mask()
1752 uint32_t mclk_mask = 0; in vega12_dpm_force_dpm_level() local
1769 ret = vega12_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); in vega12_dpm_force_dpm_level()
1773 vega12_force_clock_level(hwmgr, PP_MCLK, 1 << mclk_mask); in vega12_dpm_force_dpm_level()
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| D | vega20_hwmgr.c | 2522 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) in vega20_get_profiling_clk_mask() argument
2530 *mclk_mask = 0; in vega20_get_profiling_clk_mask()
2537 *mclk_mask = VEGA20_UMD_PSTATE_MCLK_LEVEL; in vega20_get_profiling_clk_mask()
2544 *mclk_mask = 0; in vega20_get_profiling_clk_mask()
2547 *mclk_mask = mem_dpm_table->count - 1; in vega20_get_profiling_clk_mask()
2722 uint32_t sclk_mask, mclk_mask, soc_mask; in vega20_dpm_force_dpm_level() local
2741 ret = vega20_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); in vega20_dpm_force_dpm_level()
2745 vega20_force_clock_level(hwmgr, PP_MCLK, 1 << mclk_mask); in vega20_dpm_force_dpm_level()
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| D | smu7_hwmgr.c | 3116 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *pcie_mask) in smu7_get_profiling_clk() argument
3134 *mclk_mask = golden_dpm_table->mclk_table.count - 1; in smu7_get_profiling_clk()
3137 *mclk_mask = golden_dpm_table->mclk_table.count - 2; in smu7_get_profiling_clk()
3179 *mclk_mask = 0; in smu7_get_profiling_clk()
3181 *mclk_mask = golden_dpm_table->mclk_table.count - 1; in smu7_get_profiling_clk()
3195 uint32_t mclk_mask = 0; in smu7_force_dpm_level() local
3199 smu7_get_profiling_clk(hwmgr, level, &sclk_mask, &mclk_mask, &pcie_mask); in smu7_force_dpm_level()
3215 ret = smu7_get_profiling_clk(hwmgr, level, &sclk_mask, &mclk_mask, &pcie_mask); in smu7_force_dpm_level()
3219 smu7_force_clock_level(hwmgr, PP_MCLK, 1<<mclk_mask); in smu7_force_dpm_level()
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| D | vega10_hwmgr.c | 4161 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) in vega10_get_profiling_clk_mask() argument
4171 *mclk_mask = VEGA10_UMD_PSTATE_MCLK_LEVEL; in vega10_get_profiling_clk_mask()
4179 *mclk_mask = 0; in vega10_get_profiling_clk_mask()
4189 *mclk_mask = table_info->vdd_dep_on_mclk->count - 1; in vega10_get_profiling_clk_mask()
4281 uint32_t mclk_mask = 0; in vega10_dpm_force_dpm_level() local
4285 vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); in vega10_dpm_force_dpm_level()
4301 ret = vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); in vega10_dpm_force_dpm_level()
4305 vega10_force_clock_level(hwmgr, PP_MCLK, 1<<mclk_mask); in vega10_dpm_force_dpm_level()
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