Searched refs:link_width_cntl (Results 1 – 5 of 5) sorted by relevance
| /linux-5.19.10/drivers/gpu/drm/radeon/ |
| D | rv770.c | 2032 u32 link_width_cntl, lanes, speed_cntl, tmp; in rv770_pcie_gen2_enable() local
2055 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); in rv770_pcie_gen2_enable()
2056 link_width_cntl &= ~LC_UPCONFIGURE_DIS; in rv770_pcie_gen2_enable()
2057 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); in rv770_pcie_gen2_enable()
2058 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); in rv770_pcie_gen2_enable()
2059 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) { in rv770_pcie_gen2_enable()
2060 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; in rv770_pcie_gen2_enable()
2061 link_width_cntl &= ~(LC_LINK_WIDTH_MASK | in rv770_pcie_gen2_enable()
2063 link_width_cntl |= lanes | LC_RECONFIG_NOW | in rv770_pcie_gen2_enable()
2065 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); in rv770_pcie_gen2_enable()
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| D | r300.c | 502 uint32_t link_width_cntl, mask; in rv370_set_pcie_lanes() local
537 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); in rv370_set_pcie_lanes()
539 if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) == in rv370_set_pcie_lanes()
543 link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK | in rv370_set_pcie_lanes()
547 link_width_cntl |= mask; in rv370_set_pcie_lanes()
548 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); in rv370_set_pcie_lanes()
549 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl | in rv370_set_pcie_lanes()
553 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); in rv370_set_pcie_lanes()
554 while (link_width_cntl == 0xffffffff) in rv370_set_pcie_lanes()
555 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); in rv370_set_pcie_lanes()
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| D | r600.c | 4397 u32 link_width_cntl, mask; in r600_set_pcie_lanes() local
4439 link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL); in r600_set_pcie_lanes()
4440 link_width_cntl &= ~RADEON_PCIE_LC_LINK_WIDTH_MASK; in r600_set_pcie_lanes()
4441 link_width_cntl |= mask << RADEON_PCIE_LC_LINK_WIDTH_SHIFT; in r600_set_pcie_lanes()
4442 link_width_cntl |= (RADEON_PCIE_LC_RECONFIG_NOW | in r600_set_pcie_lanes()
4445 WREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); in r600_set_pcie_lanes()
4450 u32 link_width_cntl; in r600_get_pcie_lanes() local
4464 link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL); in r600_get_pcie_lanes()
4466 …switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIF… in r600_get_pcie_lanes()
4487 u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp; in r600_pcie_gen2_enable() local
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| D | evergreen.c | 5326 u32 link_width_cntl, speed_cntl; in evergreen_pcie_gen2_enable() local
5356 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); in evergreen_pcie_gen2_enable()
5357 link_width_cntl &= ~LC_UPCONFIGURE_DIS; in evergreen_pcie_gen2_enable()
5358 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); in evergreen_pcie_gen2_enable()
5377 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); in evergreen_pcie_gen2_enable()
5380 link_width_cntl |= LC_UPCONFIGURE_DIS; in evergreen_pcie_gen2_enable()
5382 link_width_cntl &= ~LC_UPCONFIGURE_DIS; in evergreen_pcie_gen2_enable()
5383 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); in evergreen_pcie_gen2_enable()
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| /linux-5.19.10/drivers/gpu/drm/amd/amdgpu/ |
| D | si.c | 1517 u32 link_width_cntl; in si_get_pcie_lanes() local
1522 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); in si_get_pcie_lanes()
1524 switch ((link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT) { in si_get_pcie_lanes()
1542 u32 link_width_cntl, mask; in si_set_pcie_lanes() local
1571 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); in si_set_pcie_lanes()
1572 link_width_cntl &= ~LC_LINK_WIDTH_MASK; in si_set_pcie_lanes()
1573 link_width_cntl |= mask << LC_LINK_WIDTH_SHIFT; in si_set_pcie_lanes()
1574 link_width_cntl |= (LC_RECONFIG_NOW | in si_set_pcie_lanes()
1577 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); in si_set_pcie_lanes()
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