| /linux-5.19.10/tools/testing/selftests/drivers/net/mlxsw/ |
| D | ethtool_lanes.sh | 40 local lanes=$1; shift
47 ((chosen_lanes == lanes))
48 check_err $? "swp1 advertise $max_speed and $lanes, devs sync to $chosen_lanes"
65 ethtool -s $swp1 speed $max_speed lanes $unsupported_lanes $autoneg_str &> /dev/null
93 local lanes=$1; shift
97 if [[ $speed -eq ${arr[$i]} && $lanes -eq ${arr[i+1]} ]]; then
108 local lanes
117 lanes=$max_lanes
119 while [[ $lanes -ge 1 ]]; do
120 search_linkmode $max_speed $lanes "${linkmodes_params[@]}"
[all …]
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| /linux-5.19.10/drivers/staging/media/omap4iss/ |
| D | iss_csiphy.c | 36 reg |= (phy->lanes.data[i].pol ? in csiphy_lanes_config()
38 reg |= (phy->lanes.data[i].pos << in csiphy_lanes_config()
44 reg |= phy->lanes.clk.pol ? CSI2_COMPLEXIO_CFG_CLOCK_POL : 0; in csiphy_lanes_config()
45 reg |= phy->lanes.clk.pos << CSI2_COMPLEXIO_CFG_CLOCK_POSITION_SHIFT; in csiphy_lanes_config()
123 struct iss_csiphy_lanes_cfg *lanes; in omap4iss_csiphy_config() local
128 lanes = &subdevs->bus.csi2.lanecfg; in omap4iss_csiphy_config()
175 if (lanes->data[i].pos == 0) in omap4iss_csiphy_config()
178 if (lanes->data[i].pol > 1 || in omap4iss_csiphy_config()
179 lanes->data[i].pos > (csi2->phy->max_data_lanes + 1)) in omap4iss_csiphy_config()
182 if (used_lanes & (1 << lanes->data[i].pos)) in omap4iss_csiphy_config()
[all …]
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| /linux-5.19.10/arch/arm64/boot/dts/renesas/ |
| D | r8a779a0-falcon-csi-dsi.dtsi | 19 clock-lanes = <0>;
20 data-lanes = <1 2 3 4>;
38 clock-lanes = <0>;
39 data-lanes = <1 2 3 4>;
57 clock-lanes = <0>;
58 data-lanes = <1 2 3 4>;
108 clock-lanes = <0>;
109 data-lanes = <1 2 3 4>;
128 clock-lanes = <0>;
129 data-lanes = <1 2 3 4>;
[all …]
|
| D | hihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi | 18 clock-lanes = <0>;
19 data-lanes = <1 2>;
32 clock-lanes = <0>;
33 data-lanes = <1 2>;
49 clock-lanes = <0>;
50 data-lanes = <1 2>;
63 clock-lanes = <0>;
64 data-lanes = <1 2>;
|
| D | r8a774c0-ek874-mipi-2.1.dts | 38 clock-lanes = <0>;
39 data-lanes = <1 2>;
52 clock-lanes = <0>;
53 data-lanes = <1 2>;
62 clock-lanes = <0>;
63 data-lanes = <1 2>;
|
| /linux-5.19.10/Documentation/devicetree/bindings/media/ |
| D | qcom,sm8250-camss.yaml | 125 clock-lanes:
128 data-lanes:
133 - clock-lanes
134 - data-lanes
148 clock-lanes:
151 data-lanes:
156 - clock-lanes
157 - data-lanes
171 clock-lanes:
174 data-lanes:
[all …]
|
| D | ti,cal.yaml | 86 clock-lanes:
89 data-lanes:
104 clock-lanes:
107 data-lanes:
146 clock-lanes = <0>;
147 data-lanes = <1 2>;
170 clock-lanes = <0>;
171 data-lanes = <1 2>;
|
| /linux-5.19.10/drivers/gpu/drm/tegra/ |
| D | dp.c | 51 link->lanes = 0; in drm_dp_link_reset()
233 link->lanes = link->max_lanes; in drm_dp_link_probe()
346 values[1] = link->lanes; in drm_dp_link_configure()
394 static const unsigned int lanes[3] = { 1, 2, 4 }; in drm_dp_link_choose() local
402 for (i = 0; i < ARRAY_SIZE(lanes) && lanes[i] <= link->max_lanes; i++) { in drm_dp_link_choose()
412 capacity = lanes[i] * (rates[j] * 10) * 8 / 10; in drm_dp_link_choose()
416 lanes[i], rates[j], requirement, in drm_dp_link_choose()
418 link->lanes = lanes[i]; in drm_dp_link_choose()
469 unsigned int lanes = link->lanes, *vs, *pe, *pc, i; in drm_dp_link_apply_training() local
485 for (i = 0; i < lanes; i++) in drm_dp_link_apply_training()
[all …]
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| /linux-5.19.10/drivers/media/platform/ti/omap3isp/ |
| D | ispcsiphy.c | 167 struct isp_csiphy_lanes_cfg *lanes; in omap3isp_csiphy_config() local
175 lanes = &buscfg->bus.ccp2.lanecfg; in omap3isp_csiphy_config()
178 lanes = &buscfg->bus.csi2.lanecfg; in omap3isp_csiphy_config()
187 if (lanes->data[i].pol > 1 || lanes->data[i].pos > 3) in omap3isp_csiphy_config()
190 if (used_lanes & (1 << lanes->data[i].pos)) in omap3isp_csiphy_config()
193 used_lanes |= 1 << lanes->data[i].pos; in omap3isp_csiphy_config()
196 if (lanes->clk.pol > 1 || lanes->clk.pos > 3) in omap3isp_csiphy_config()
199 if (lanes->clk.pos == 0 || used_lanes & (1 << lanes->clk.pos)) in omap3isp_csiphy_config()
245 reg |= (lanes->data[i].pol << in omap3isp_csiphy_config()
247 reg |= (lanes->data[i].pos << in omap3isp_csiphy_config()
[all …]
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| /linux-5.19.10/drivers/gpu/drm/bridge/adv7511/ |
| D | adv7533.c | 43 clock_div_by_lanes[dsi->lanes - 2] << 3); in adv7511_dsi_config_timing_gen()
74 regmap_write(adv->regmap_cec, 0x1c, dsi->lanes << 4); in adv7533_dsi_power_on()
106 int lanes, ret; in adv7533_mode_set() local
112 lanes = 4; in adv7533_mode_set()
114 lanes = 3; in adv7533_mode_set()
116 if (lanes != dsi->lanes) { in adv7533_mode_set()
118 dsi->lanes = lanes; in adv7533_mode_set()
164 dsi->lanes = adv->num_dsi_lanes; in adv7533_attach_dsi()
|
| /linux-5.19.10/drivers/net/ethernet/netronome/nfp/ |
| D | nfp_devlink.c | 39 nfp_devlink_set_lanes(struct nfp_pf *pf, unsigned int idx, unsigned int lanes) in nfp_devlink_set_lanes() argument
48 ret = __nfp_eth_set_split(nsp, lanes); in nfp_devlink_set_lanes()
69 unsigned int lanes; in nfp_devlink_port_split() local
82 lanes = eth_port.port_lanes / count; in nfp_devlink_port_split()
83 if (eth_port.lanes == 10 && count == 2) in nfp_devlink_port_split()
84 lanes = 8 / count; in nfp_devlink_port_split()
86 return nfp_devlink_set_lanes(pf, eth_port.index, lanes); in nfp_devlink_port_split()
95 unsigned int lanes; in nfp_devlink_port_unsplit() local
108 lanes = eth_port.port_lanes; in nfp_devlink_port_unsplit()
110 lanes = 10; in nfp_devlink_port_unsplit()
[all …]
|
| /linux-5.19.10/Documentation/devicetree/bindings/media/i2c/ |
| D | adv748x.yaml | 83 clock-lanes:
86 data-lanes:
91 - clock-lanes
92 - data-lanes
106 clock-lanes:
109 data-lanes:
113 - clock-lanes
114 - data-lanes
195 clock-lanes = <0>;
196 data-lanes = <1 2 3 4>;
[all …]
|
| /linux-5.19.10/drivers/gpu/drm/omapdrm/dss/ |
| D | hdmi_common.c | 20 u32 lanes[8]; in hdmi_parse_lanes_of() local
22 if (len / sizeof(u32) != ARRAY_SIZE(lanes)) { in hdmi_parse_lanes_of()
27 r = of_property_read_u32_array(ep, "lanes", lanes, in hdmi_parse_lanes_of()
28 ARRAY_SIZE(lanes)); in hdmi_parse_lanes_of()
34 r = hdmi_phy_parse_lanes(phy, lanes); in hdmi_parse_lanes_of()
|
| /linux-5.19.10/drivers/video/fbdev/omap2/omapfb/dss/ |
| D | hdmi_common.c | 20 u32 lanes[8]; in hdmi_parse_lanes_of() local
22 if (len / sizeof(u32) != ARRAY_SIZE(lanes)) { in hdmi_parse_lanes_of()
27 r = of_property_read_u32_array(ep, "lanes", lanes, in hdmi_parse_lanes_of()
28 ARRAY_SIZE(lanes)); in hdmi_parse_lanes_of()
34 r = hdmi_phy_parse_lanes(phy, lanes); in hdmi_parse_lanes_of()
|
| /linux-5.19.10/tools/testing/selftests/net/ |
| D | devlink_port_split.py | 85 lanes = values['lanes']
87 lanes = 0
88 return lanes
148 def exists_and_lanes(ports, lanes, dev): argument
160 if max_lanes != lanes:
162 % (port, lanes, max_lanes))
202 def split_splittable_port(port, k, lanes, dev): argument
217 test(exists_and_lanes(new_split_group, lanes/k, dev),
|
| /linux-5.19.10/drivers/nubus/ |
| D | proc.c | 73 int lanes = board->lanes; in nubus_proc_add_rsrc_dir() local
78 return proc_mkdir_data(name, 0555, procdir, (void *)lanes); in nubus_proc_add_rsrc_dir()
120 int lanes = (int)proc_get_parent_data(inode); in nubus_proc_rsrc_show() local
123 if (!lanes) in nubus_proc_rsrc_show()
126 ent.mask = lanes; in nubus_proc_rsrc_show()
|
| /linux-5.19.10/Documentation/devicetree/bindings/media/xilinx/ |
| D | xlnx,csi2rxss.yaml | 88 xlnx,en-active-lanes:
91 Present if the number of active lanes can be re-configured at
92 runtime in the Protocol Configuration Register. Otherwise all lanes,
115 data-lanes:
121 1 2 - For 2 lanes enabled in IP.
122 1 2 3 - For 3 lanes enabled in IP.
123 1 2 3 4 - For 4 lanes enabled in IP.
131 - data-lanes
180 xlnx,en-active-lanes;
195 data-lanes = <1 2 3 4>;
|
| /linux-5.19.10/drivers/phy/cadence/ |
| D | cdns-dphy-rx.c | 119 unsigned int lanes) in cdns_dphy_rx_wait_lane_ready() argument
135 for (i = 0; i < lanes; i++) { in cdns_dphy_rx_wait_lane_ready()
149 unsigned int reg, lanes = opts->mipi_dphy.lanes; in cdns_dphy_rx_configure() local
153 if (lanes < DPHY_LANES_MIN || lanes > DPHY_LANES_MAX) in cdns_dphy_rx_configure()
173 ret = cdns_dphy_rx_wait_lane_ready(dphy, lanes); in cdns_dphy_rx_configure()
|
| /linux-5.19.10/Documentation/devicetree/bindings/pci/ |
| D | nvidia,tegra20-pcie.txt | 104 - If lanes 0 to 3 are used:
107 - If lanes 4 or 5 are used:
148 - nvidia,num-lanes: Number of lanes to use for this port. Valid combinations
150 - Root port 0 uses 4 lanes, root port 1 is unused.
151 - Both root ports use 2 lanes.
157 number of lanes in the nvidia,num-lanes property. Entries are of the form
158 "pcie-N": where N ranges from 0 to the value specified in nvidia,num-lanes.
210 nvidia,num-lanes = <2>;
224 nvidia,num-lanes = <2>;
316 nvidia,num-lanes = <2>;
[all …]
|
| /linux-5.19.10/arch/arm64/boot/dts/marvell/ |
| D | cn9132-db.dtsi | 66 * lanes not being connected. Prevent the port for being
107 /* Generic PHY, providing serdes lanes */
155 num-lanes = <2>;
157 /* Generic PHY, providing serdes lanes */
165 num-lanes = <1>;
167 /* Generic PHY, providing serdes lanes */
176 /* Generic PHY, providing serdes lanes */
223 /* Generic PHY, providing serdes lanes */
|
| /linux-5.19.10/Documentation/devicetree/bindings/phy/ |
| D | phy-cadence-sierra.yaml | 83 Each group of PHY lanes with a single master lane should be represented as
97 Contains list of resets, one per lane, to get all the link lanes out of reset.
104 Specifies the type of PHY for which the group of PHY lanes is used.
109 cdns,num-lanes:
111 Number of lanes in this group. The group is made up of consecutive lanes.
162 cdns,num-lanes = <2>;
169 cdns,num-lanes = <1>;
|
| D | phy-cadence-torrent.yaml | 81 Each group of PHY lanes with a single master lane should be represented as a sub-node.
93 Contains list of resets, one per lane, to get all the link lanes out of reset.
100 Specifies the type of PHY for which the group of PHY lanes is used.
106 cdns,num-lanes:
108 Number of lanes.
134 - cdns,num-lanes
176 cdns,num-lanes = <4>;
204 cdns,num-lanes = <2>;
213 cdns,num-lanes = <1>;
|
| D | nvidia,tegra124-xusb-padctl.txt | 4 The Tegra XUSB pad controller manages a set of I/O lanes (with differential
7 documentation. Each such "pad" may control either one or multiple lanes,
8 and thus contains any logic common to all its lanes. Each lane can be
11 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
12 super-speed USB. Other lanes are for various types of low-speed, full-speed
15 ports (e.g. PCIe) and the lanes.
81 the pad and any of its lanes, this property must be set to "okay".
128 Each pad node has a child named "lanes" that contains one or more children of
129 its own, each representing one of the lanes controlled by the pad.
284 lanes {
[all …]
|
| /linux-5.19.10/drivers/gpu/drm/rockchip/ |
| D | cdn-dp-core.c | 156 u8 lanes; in cdn_dp_get_port_lanes() local
163 lanes = 2; in cdn_dp_get_port_lanes()
165 lanes = 4; in cdn_dp_get_port_lanes()
167 lanes = 0; in cdn_dp_get_port_lanes()
170 return lanes; in cdn_dp_get_port_lanes()
190 int i, lanes; in cdn_dp_connected_port() local
194 lanes = cdn_dp_get_port_lanes(port); in cdn_dp_connected_port()
195 if (lanes) in cdn_dp_connected_port()
292 u8 lanes, bpc; in cdn_dp_connector_mode_valid() local
312 source_max = dp->lanes; in cdn_dp_connector_mode_valid()
[all …]
|
| /linux-5.19.10/arch/arm/boot/dts/ |
| D | omap3-n9.dts | 30 clock-lanes = <0>;
31 data-lanes = <1 2>;
53 clock-lanes = <2>;
54 data-lanes = <1 3>;
|