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Searched refs:ixAZALIA_CRC1_CHANNEL7 (Results 1 – 15 of 15) sorted by relevance

/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_8_0_d.h5470 #define ixAZALIA_CRC1_CHANNEL7 0x7 macro
Ddce_10_0_d.h6741 #define ixAZALIA_CRC1_CHANNEL7 0x7 macro
Ddce_11_0_d.h6903 #define ixAZALIA_CRC1_CHANNEL7 0x7 macro
Ddce_11_2_d.h8248 #define ixAZALIA_CRC1_CHANNEL7 0x7 macro
Ddce_12_0_offset.h18127 #define ixAZALIA_CRC1_CHANNEL7 … macro
/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_3_0_3_offset.h7410 #define ixAZALIA_CRC1_CHANNEL7 … macro
Ddcn_3_0_1_offset.h12253 #define ixAZALIA_CRC1_CHANNEL7 … macro
Ddcn_1_0_offset.h13097 #define ixAZALIA_CRC1_CHANNEL7 … macro
Ddcn_2_1_0_offset.h12857 #define ixAZALIA_CRC1_CHANNEL7 … macro
Ddcn_3_1_2_offset.h14067 #define ixAZALIA_CRC1_CHANNEL7 … macro
Ddcn_3_1_5_offset.h14173 #define ixAZALIA_CRC1_CHANNEL7 … macro
Ddcn_3_0_2_offset.h15142 #define ixAZALIA_CRC1_CHANNEL7 … macro
Ddcn_3_1_6_offset.h14664 #define ixAZALIA_CRC1_CHANNEL7 … macro
Ddcn_2_0_0_offset.h16521 #define ixAZALIA_CRC1_CHANNEL7 … macro
Ddcn_3_0_0_offset.h16864 #define ixAZALIA_CRC1_CHANNEL7 … macro