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Searched refs:ixAZALIA_CRC1_CHANNEL5 (Results 1 – 15 of 15) sorted by relevance

/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_8_0_d.h5468 #define ixAZALIA_CRC1_CHANNEL5 0x5 macro
Ddce_10_0_d.h6739 #define ixAZALIA_CRC1_CHANNEL5 0x5 macro
Ddce_11_0_d.h6901 #define ixAZALIA_CRC1_CHANNEL5 0x5 macro
Ddce_11_2_d.h8246 #define ixAZALIA_CRC1_CHANNEL5 0x5 macro
Ddce_12_0_offset.h18125 #define ixAZALIA_CRC1_CHANNEL5 … macro
/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_3_0_3_offset.h7408 #define ixAZALIA_CRC1_CHANNEL5 … macro
Ddcn_3_0_1_offset.h12251 #define ixAZALIA_CRC1_CHANNEL5 … macro
Ddcn_1_0_offset.h13095 #define ixAZALIA_CRC1_CHANNEL5 … macro
Ddcn_2_1_0_offset.h12855 #define ixAZALIA_CRC1_CHANNEL5 … macro
Ddcn_3_1_2_offset.h14065 #define ixAZALIA_CRC1_CHANNEL5 … macro
Ddcn_3_1_5_offset.h14171 #define ixAZALIA_CRC1_CHANNEL5 … macro
Ddcn_3_0_2_offset.h15140 #define ixAZALIA_CRC1_CHANNEL5 … macro
Ddcn_3_1_6_offset.h14662 #define ixAZALIA_CRC1_CHANNEL5 … macro
Ddcn_2_0_0_offset.h16519 #define ixAZALIA_CRC1_CHANNEL5 … macro
Ddcn_3_0_0_offset.h16862 #define ixAZALIA_CRC1_CHANNEL5 … macro