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Searched refs:ixAZALIA_CRC1_CHANNEL3 (Results 1 – 15 of 15) sorted by relevance

/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_8_0_d.h5466 #define ixAZALIA_CRC1_CHANNEL3 0x3 macro
Ddce_10_0_d.h6737 #define ixAZALIA_CRC1_CHANNEL3 0x3 macro
Ddce_11_0_d.h6899 #define ixAZALIA_CRC1_CHANNEL3 0x3 macro
Ddce_11_2_d.h8244 #define ixAZALIA_CRC1_CHANNEL3 0x3 macro
Ddce_12_0_offset.h18123 #define ixAZALIA_CRC1_CHANNEL3 … macro
/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_3_0_3_offset.h7406 #define ixAZALIA_CRC1_CHANNEL3 … macro
Ddcn_3_0_1_offset.h12249 #define ixAZALIA_CRC1_CHANNEL3 … macro
Ddcn_1_0_offset.h13093 #define ixAZALIA_CRC1_CHANNEL3 … macro
Ddcn_2_1_0_offset.h12853 #define ixAZALIA_CRC1_CHANNEL3 … macro
Ddcn_3_1_2_offset.h14063 #define ixAZALIA_CRC1_CHANNEL3 … macro
Ddcn_3_1_5_offset.h14169 #define ixAZALIA_CRC1_CHANNEL3 … macro
Ddcn_3_0_2_offset.h15138 #define ixAZALIA_CRC1_CHANNEL3 … macro
Ddcn_3_1_6_offset.h14660 #define ixAZALIA_CRC1_CHANNEL3 … macro
Ddcn_2_0_0_offset.h16517 #define ixAZALIA_CRC1_CHANNEL3 … macro
Ddcn_3_0_0_offset.h16860 #define ixAZALIA_CRC1_CHANNEL3 … macro