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Searched refs:ixAZALIA_CRC1_CHANNEL2 (Results 1 – 15 of 15) sorted by relevance

/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_8_0_d.h5465 #define ixAZALIA_CRC1_CHANNEL2 0x2 macro
Ddce_10_0_d.h6736 #define ixAZALIA_CRC1_CHANNEL2 0x2 macro
Ddce_11_0_d.h6898 #define ixAZALIA_CRC1_CHANNEL2 0x2 macro
Ddce_11_2_d.h8243 #define ixAZALIA_CRC1_CHANNEL2 0x2 macro
Ddce_12_0_offset.h18122 #define ixAZALIA_CRC1_CHANNEL2 … macro
/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_3_0_3_offset.h7405 #define ixAZALIA_CRC1_CHANNEL2 … macro
Ddcn_3_0_1_offset.h12248 #define ixAZALIA_CRC1_CHANNEL2 … macro
Ddcn_1_0_offset.h13092 #define ixAZALIA_CRC1_CHANNEL2 … macro
Ddcn_2_1_0_offset.h12852 #define ixAZALIA_CRC1_CHANNEL2 … macro
Ddcn_3_1_2_offset.h14062 #define ixAZALIA_CRC1_CHANNEL2 … macro
Ddcn_3_1_5_offset.h14168 #define ixAZALIA_CRC1_CHANNEL2 … macro
Ddcn_3_0_2_offset.h15137 #define ixAZALIA_CRC1_CHANNEL2 … macro
Ddcn_3_1_6_offset.h14659 #define ixAZALIA_CRC1_CHANNEL2 … macro
Ddcn_2_0_0_offset.h16516 #define ixAZALIA_CRC1_CHANNEL2 … macro
Ddcn_3_0_0_offset.h16859 #define ixAZALIA_CRC1_CHANNEL2 … macro