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Searched refs:ixAZALIA_CRC1_CHANNEL0 (Results 1 – 15 of 15) sorted by relevance

/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_8_0_d.h5463 #define ixAZALIA_CRC1_CHANNEL0 0x0 macro
Ddce_10_0_d.h6734 #define ixAZALIA_CRC1_CHANNEL0 0x0 macro
Ddce_11_0_d.h6896 #define ixAZALIA_CRC1_CHANNEL0 0x0 macro
Ddce_11_2_d.h8241 #define ixAZALIA_CRC1_CHANNEL0 0x0 macro
Ddce_12_0_offset.h18120 #define ixAZALIA_CRC1_CHANNEL0 … macro
/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_3_0_3_offset.h7403 #define ixAZALIA_CRC1_CHANNEL0 … macro
Ddcn_3_0_1_offset.h12246 #define ixAZALIA_CRC1_CHANNEL0 … macro
Ddcn_1_0_offset.h13090 #define ixAZALIA_CRC1_CHANNEL0 … macro
Ddcn_2_1_0_offset.h12850 #define ixAZALIA_CRC1_CHANNEL0 … macro
Ddcn_3_1_2_offset.h14060 #define ixAZALIA_CRC1_CHANNEL0 … macro
Ddcn_3_1_5_offset.h14166 #define ixAZALIA_CRC1_CHANNEL0 … macro
Ddcn_3_0_2_offset.h15135 #define ixAZALIA_CRC1_CHANNEL0 … macro
Ddcn_3_1_6_offset.h14657 #define ixAZALIA_CRC1_CHANNEL0 … macro
Ddcn_2_0_0_offset.h16514 #define ixAZALIA_CRC1_CHANNEL0 … macro
Ddcn_3_0_0_offset.h16857 #define ixAZALIA_CRC1_CHANNEL0 … macro