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Searched refs:io_p2v (Results 1 – 18 of 18) sorted by relevance

/linux-5.19.10/arch/arm/mach-pxa/
Dregs-ost.h13 #define OSMR0 io_p2v(0x40A00000) /* */
14 #define OSMR1 io_p2v(0x40A00004) /* */
15 #define OSMR2 io_p2v(0x40A00008) /* */
16 #define OSMR3 io_p2v(0x40A0000C) /* */
17 #define OSMR4 io_p2v(0x40A00080) /* */
18 #define OSCR io_p2v(0x40A00010) /* OS Timer Counter Register */
19 #define OSCR4 io_p2v(0x40A00040) /* OS Timer Counter Register */
20 #define OMCR4 io_p2v(0x40A000C0) /* */
21 #define OSSR io_p2v(0x40A00014) /* OS Timer Status Register */
22 #define OWER io_p2v(0x40A00018) /* OS Timer Watchdog Enable Register */
[all …]
Dgeneric.c52 pxa25x_clocks_init(io_p2v(0x41300000)); in pxa_timer_init()
54 pxa27x_clocks_init(io_p2v(0x41300000)); in pxa_timer_init()
56 pxa3xx_clocks_init(io_p2v(0x41340000), io_p2v(0x41350000)); in pxa_timer_init()
57 pxa_timer_nodt_init(IRQ_OST0, io_p2v(0x40a00000)); in pxa_timer_init()
Dpxa-regs.h32 #define io_p2v(x) IOMEM(0xf2000000 + ((x) & 0x01ffffff) + (((x) & 0x1c000000) >> 1)) macro
35 # define __REG(x) (*((volatile u32 __iomem *)io_p2v(x)))
46 # define __REG(x) io_p2v(x)
Dpxa2xx-regs.h134 #define CCCR io_p2v(0x41300000) /* Core Clock Configuration Register */
135 #define CCSR io_p2v(0x4130000C) /* Core Clock Status Register */
136 #define CKEN io_p2v(0x41300004) /* Clock Enable Register */
137 #define OSCC io_p2v(0x41300008) /* Oscillator Configuration Register */
Dirq.c173 pxa_irq_base = io_p2v(0x40d00000); in pxa_init_irq()
258 pxa_irq_base = io_p2v(res.start); in pxa_dt_irq_init()
Dpxa300.c87 mfp_init_base(io_p2v(MFPR_BASE)); in pxa300_init()
Dpxa320.c81 mfp_init_base(io_p2v(MFPR_BASE)); in pxa320_init()
Dpxa3xx-regs.h18 #define OSCC io_p2v(0x41350000) /* Oscillator Configuration Register */
Dpxa27x-udc.h180 #define PUDCDN(x) (volatile u32 *)(io_p2v(PHYS_UDCDN((x))))
Dpxa930.c203 mfp_init_base(io_p2v(MFPR_BASE)); in pxa930_init()
/linux-5.19.10/arch/arm/mach-lpc32xx/
Dlpc32xx.h121 #define _PMREG(x) io_p2v(LPC32XX_CLK_PM_BASE +\
576 #define LPC32XX_INTC_MASK(x) io_p2v((x) + 0x00)
577 #define LPC32XX_INTC_RAW_STAT(x) io_p2v((x) + 0x04)
578 #define LPC32XX_INTC_STAT(x) io_p2v((x) + 0x08)
579 #define LPC32XX_INTC_POLAR(x) io_p2v((x) + 0x0C)
580 #define LPC32XX_INTC_ACT_TYPE(x) io_p2v((x) + 0x10)
581 #define LPC32XX_INTC_TYPE(x) io_p2v((x) + 0x14)
586 #define LPC32XX_TIMER_IR(x) io_p2v((x) + 0x00)
587 #define LPC32XX_TIMER_TCR(x) io_p2v((x) + 0x04)
588 #define LPC32XX_TIMER_TC(x) io_p2v((x) + 0x08)
[all …]
Dcommon.c41 iramptr1 = io_p2v(LPC32XX_IRAM_BASE); in lpc32xx_return_iram()
42 iramptr2 = io_p2v(LPC32XX_IRAM_BASE + LPC32XX_IRAM_BANK_SIZE); in lpc32xx_return_iram()
59 *mapbase = io_p2v(LPC32XX_IRAM_BASE); in lpc32xx_return_iram()
Dpm.c124 #define EMC_CTRL_REG io_p2v(LPC32XX_EMC_BASE + EMC_DYN_MEM_CTRL_OFS)
/linux-5.19.10/arch/arm/mach-sa1100/include/mach/
Dhardware.h35 #define io_p2v( x ) \ macro
40 #define __MREG(x) IOMEM(io_p2v(x))
44 # define __REG(x) (*((volatile unsigned long __iomem *)io_p2v(x)))
49 # define __REG(x) io_p2v(x)
DSA-1100.h834 #define OSMR0 io_p2v(0x90000000) /* OS timer Match Reg. 0 */
835 #define OSMR1 io_p2v(0x90000004) /* OS timer Match Reg. 1 */
836 #define OSMR2 io_p2v(0x90000008) /* OS timer Match Reg. 2 */
837 #define OSMR3 io_p2v(0x9000000c) /* OS timer Match Reg. 3 */
838 #define OSCR io_p2v(0x90000010) /* OS timer Counter Reg. */
839 #define OSSR io_p2v(0x90000014) /* OS timer Status Reg. */
840 #define OWER io_p2v(0x90000018) /* OS timer Watch-dog Enable Reg. */
841 #define OIER io_p2v(0x9000001C) /* OS timer Interrupt Enable Reg. */
/linux-5.19.10/arch/arm/mach-ux500/
Ddb8500-regs.h191 #define io_p2v(n) __io_address(n) macro
/linux-5.19.10/arch/arm/mach-sa1100/
Dgeneric.c411 pxa_timer_nodt_init(IRQ_OST0, io_p2v(0x90000000)); in sa1100_timer_init()
Dassabet.c637 unsigned long virt = (unsigned long)io_p2v(phys); in map_sa1100_gpio_regs()