Searched refs:imx_readl (Results 1 – 11 of 11) sorted by relevance
61 value = imx_readl(tzic_base + TZIC_INTSEC0(index)) | mask; in tzic_set_irq_fiq()85 imx_writel(imx_readl(tzic_base + TZIC_ENSET0(idx)), in tzic_irq_resume()131 stat = imx_readl(tzic_base + TZIC_HIPND(i)) & in tzic_handle_irq()132 imx_readl(tzic_base + TZIC_INTSEC0(i)); in tzic_handle_irq()160 i = imx_readl(tzic_base + TZIC_INTCNTL); in tzic_init_dt()212 if (unlikely(imx_readl(tzic_base + TZIC_DSMINT) == 0)) in tzic_enable_wake()216 imx_writel(imx_readl(tzic_base + TZIC_ENSET0(i)), in tzic_enable_wake()
60 irqt = imx_readl(avic_base + AVIC_INTTYPEL) & ~(1 << hwirq); in avic_set_irq_fiq()64 irqt = imx_readl(avic_base + AVIC_INTTYPEH) & ~(1 << hwirq); in avic_set_irq_fiq()88 avic_saved_mask_reg[idx] = imx_readl(avic_base + ct->regs.mask); in avic_irq_suspend()153 nivector = imx_readl(avic_base + AVIC_NIVECSR) >> 16; in avic_handle_irq()
150 plat_lpc = imx_readl(cortex_base + MXC_CORTEXA8_PLAT_LPC) & in mx5_cpu_lp_set()152 ccm_clpcr = imx_readl(ccm_base + MXC_CCM_CLPCR) & in mx5_cpu_lp_set()154 arm_srpgcr = imx_readl(gpc_base + MXC_SRPG_ARM_SRPGCR) & in mx5_cpu_lp_set()156 empgc0 = imx_readl(gpc_base + MXC_SRPG_EMPGC0_SRPGCR) & in mx5_cpu_lp_set()158 empgc1 = imx_readl(gpc_base + MXC_SRPG_EMPGC1_SRPGCR) & in mx5_cpu_lp_set()
94 int reg = imx_readl(mx3_ccm_base + MXC_CCM_CCMR); in imx31_idle()130 int reg = imx_readl(mx3_ccm_base + MXC_CCM_CCMR); in imx35_idle()
26 rev = imx_readl(iim_base + MXC_IIMSREV); in mx35_read_cpu_rev()
31 cscr = imx_readl(ccm_base); in mx27_suspend_enter()
37 val = imx_readl(ccm_base + SYSCTRL_OFFSET + SYS_CHIP_ID); in mx27_read_cpu_rev()
82 #define imx_readl readl_relaxed macro
57 reg = imx_readl(base + 0x50) & 0x00FFFFFF; in imx_set_aips()
41 imx_writel(imx_readl(hsc_addr + 0x800) | 0x30ff, hsc_addr + 0x800); in imx51_ipu_mipi_setup()
45 srev = imx_readl(iim_base + MXC_IIMSREV); in mx31_read_cpu_rev()