/linux-5.19.10/drivers/gpu/drm/i915/display/ |
D | intel_dsb.c | 227 i915_ggtt_offset(dsb->vma)); in intel_dsb_commit() 241 i915_ggtt_offset(dsb->vma), tail); in intel_dsb_commit() 243 i915_ggtt_offset(dsb->vma) + tail); in intel_dsb_commit()
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D | intel_overlay.c | 848 iowrite32(i915_ggtt_offset(vma) + params->offset_Y, ®s->OBUF_0Y); in intel_overlay_do_put_image() 865 iowrite32(i915_ggtt_offset(vma) + params->offset_U, in intel_overlay_do_put_image() 867 iowrite32(i915_ggtt_offset(vma) + params->offset_V, in intel_overlay_do_put_image() 1366 overlay->flip_addr = i915_ggtt_offset(vma); in get_registers()
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D | intel_fbdev.c | 308 i915_ggtt_offset(vma)); in intelfb_create()
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/linux-5.19.10/drivers/gpu/drm/i915/gt/ |
D | intel_lrc.c | 790 const u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma); in init_wa_bb_regs() 799 i915_ggtt_offset(wa_ctx->vma) + in init_wa_bb_regs() 956 return i915_ggtt_offset(ce->state) + context_wa_bb_offset(ce); in lrc_indirect_bb() 1165 *cs++ = i915_ggtt_offset(ce->state) + LRC_STATE_OFFSET + in gen12_emit_timestamp_wa() 1193 *cs++ = i915_ggtt_offset(ce->state) + LRC_STATE_OFFSET + in gen12_emit_restore_scratch() 1209 *cs++ = i915_ggtt_offset(ce->state) + LRC_STATE_OFFSET + in gen12_emit_cmd_buf_wa() 1362 return i915_ggtt_offset(ce->state) | desc; in lrc_descriptor() 1375 regs[CTX_RING_START] = i915_ggtt_offset(ring->vma); in lrc_update_regs() 1418 if (regs[CTX_RING_START] != i915_ggtt_offset(ring->vma)) { in lrc_check_regs() 1422 i915_ggtt_offset(ring->vma)); in lrc_check_regs() [all …]
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D | selftest_lrc.c | 78 i915_ggtt_offset(ce->engine->status_page.vma) + in emit_semaphore_signal() 437 *cs++ = i915_ggtt_offset(scratch) + RING_START_IDX * sizeof(u32); in __live_lrc_state() 440 expected[RING_START_IDX] = i915_ggtt_offset(ce->ring->vma); in __live_lrc_state() 444 *cs++ = i915_ggtt_offset(scratch) + RING_TAIL_IDX * sizeof(u32); in __live_lrc_state() 561 i915_ggtt_offset(ce->engine->status_page.vma) + in __gpr_read() 592 *cs++ = i915_ggtt_offset(scratch) + n * sizeof(u32); in __gpr_read() 738 i915_ggtt_offset(ce->engine->status_page.vma) + in create_timestamp() 1099 *cs++ = i915_ggtt_offset(ce->engine->status_page.vma) + in record_registers() 1221 *cs++ = i915_ggtt_offset(ce->engine->status_page.vma) + in poison_registers() 1534 *cs++ = i915_ggtt_offset(ce->state) + in emit_indirect_ctx_bb_canary()
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D | intel_timeline.c | 209 i915_ggtt_offset(tl->hwsp_ggtt) + in intel_timeline_pin() 317 tl->hwsp_offset = i915_ggtt_offset(tl->hwsp_ggtt) + next_ofs; in __intel_timeline_get_seqno() 354 *hwsp = i915_ggtt_offset(tl->hwsp_ggtt) + in intel_timeline_read_hwsp()
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D | intel_context_sseu.c | 27 offset = i915_ggtt_offset(ce->state) + in gen8_emit_rpcs_config()
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D | selftest_mocs.c | 237 offset = i915_ggtt_offset(vma); in check_mocs_engine() 242 offset -= i915_ggtt_offset(vma); in check_mocs_engine()
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D | intel_ring_submission.c | 135 set_hwsp(engine, i915_ggtt_offset(engine->status_page.vma)); in ring_setup_status_page() 219 ENGINE_WRITE_FW(engine, RING_START, i915_ggtt_offset(ring->vma)); in xcs_resume() 267 i915_ggtt_offset(ring->vma)); in xcs_resume() 753 *cs++ = i915_ggtt_offset(engine->kernel_context->state) | in mi_set_context() 760 *cs++ = i915_ggtt_offset(ce->state) | flags; in mi_set_context()
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D | intel_gt.h | 79 return i915_ggtt_offset(gt->scratch) + field; in intel_gt_scratch_offset()
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D | intel_renderstate.c | 89 so->batch_offset = i915_ggtt_offset(so->vma); in render_state_setup()
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D | selftest_timeline.c | 850 w->addr = i915_ggtt_offset(vma); in setup_watcher() 885 w->addr = i915_ggtt_offset(w->vma); in create_watcher() 899 GEM_BUG_ON(w->addr - i915_ggtt_offset(w->vma) > w->vma->size); in check_watcher() 912 end = (w->addr - i915_ggtt_offset(w->vma)) / sizeof(*w->map); in check_watcher()
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D | gen8_engine_cs.c | 326 return (i915_ggtt_offset(engine->status_page.vma) + in preempt_address() 644 return i915_ggtt_offset(rq->context->state) + in ccs_semaphore_offset()
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D | selftest_execlists.c | 837 *cs++ = i915_ggtt_offset(vma) + 4 * idx; in emit_semaphore_chain() 842 *cs++ = i915_ggtt_offset(vma) + 4 * (idx - 1); in emit_semaphore_chain() 911 *cs++ = i915_ggtt_offset(vma) + 4 * (idx - 1); in release_queue() 1056 i915_ggtt_offset(ce->engine->status_page.vma) + in create_rewinder() 1618 *cs++ = i915_ggtt_offset(vma); in live_busywait_preempt() 1629 *cs++ = i915_ggtt_offset(vma); in live_busywait_preempt() 1668 *cs++ = i915_ggtt_offset(vma); in live_busywait_preempt() 3231 *cs++ = i915_ggtt_offset(global); in preempt_user() 4254 *cs++ = i915_ggtt_offset(scratch) + n * sizeof(u32); in preserved_virtual_engine()
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D | selftest_engine_pm.c | 77 u32 offset = i915_ggtt_offset(engine->status_page.vma); in __measure_timestamps()
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D | intel_context.c | 263 i915_ggtt_offset(ce->ring->vma), in __intel_context_do_pin_ww()
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D | intel_engine_cs.c | 1692 i915_ggtt_offset(rq->ring->vma), in print_ring() 1973 i915_ggtt_offset(rq->ring->vma)); in engine_dump_request()
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/linux-5.19.10/drivers/gpu/drm/i915/gem/selftests/ |
D | i915_gem_coherency.c | 226 *cs++ = lower_32_bits(i915_ggtt_offset(vma) + offset); in gpu_set() 227 *cs++ = upper_32_bits(i915_ggtt_offset(vma) + offset); in gpu_set() 232 *cs++ = i915_ggtt_offset(vma) + offset; in gpu_set() 236 *cs++ = i915_ggtt_offset(vma) + offset; in gpu_set()
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/linux-5.19.10/drivers/gpu/drm/i915/selftests/ |
D | i915_perf.c | 239 i915_ggtt_offset(stream->noa_wait), 0, in live_noa_delay() 346 i915_ggtt_offset(stream->noa_wait), 0, in live_noa_gpr() 372 *cs++ = i915_ggtt_offset(rq->engine->status_page.vma) + in live_noa_gpr()
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/linux-5.19.10/drivers/gpu/drm/i915/ |
D | i915_perf.c | 464 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma); in oa_buffer_check_unlocked() 654 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma); in gen8_append_oa_reports() 947 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma); in gen7_append_oa_reports() 1258 stream->specific_ctx_id = i915_ggtt_offset(ce->state); in oa_get_render_ctx_id() 1408 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma); in gen7_init_oa_buffer() 1454 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma); in gen8_init_oa_buffer() 1508 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma); in gen12_init_oa_buffer() 1752 *cs++ = i915_ggtt_offset(vma) + (ts0 - batch) * 4; in alloc_noa_wait() 1789 *cs++ = i915_ggtt_offset(vma) + (jump - batch) * 4; in alloc_noa_wait() 1912 *cs++ = i915_ggtt_offset(stream->noa_wait); in alloc_oa_config_buffer() [all …]
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D | i915_vma.h | 127 static inline u32 i915_ggtt_offset(const struct i915_vma *vma) in i915_ggtt_offset() function
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D | i915_gem.c | 333 node->start = i915_ggtt_offset(vma); in i915_gem_gtt_prepare()
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/linux-5.19.10/drivers/gpu/drm/i915/gt/uc/ |
D | intel_guc.h | 335 u32 offset = i915_ggtt_offset(vma); in intel_guc_ggtt_offset()
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D | intel_guc_submission.c | 2530 desc->process_desc = i915_ggtt_offset(ce->state) + in prepare_context_registration_info_v69() 2532 desc->wq_addr = i915_ggtt_offset(ce->state) + in prepare_context_registration_info_v69() 2603 wq_desc_offset = i915_ggtt_offset(ce->state) + in prepare_context_registration_info_v70() 2605 wq_base_offset = i915_ggtt_offset(ce->state) + in prepare_context_registration_info_v70() 2704 if (i915_ggtt_offset(ce->state) != in __guc_context_pin() 3948 i915_ggtt_offset(engine->status_page.vma)); in setup_hwsp() 4764 return i915_ggtt_offset(ce->state) + in get_children_go_addr() 4774 return i915_ggtt_offset(ce->state) + in get_children_join_addr()
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/linux-5.19.10/drivers/gpu/drm/i915/gvt/ |
D | scheduler.c | 569 bb->bb_start_cmd_va[1] = i915_ggtt_offset(bb->vma); in prepare_shadow_batch_buffer() 642 wa_ctx->indirect_ctx.shadow_gma = i915_ggtt_offset(vma); in prepare_shadow_wa_ctx()
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