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Searched refs:graphic_level (Results 1 – 3 of 3) sorted by relevance

/linux-5.19.10/drivers/gpu/drm/amd/pm/powerplay/smumgr/
Diceland_smumgr.c893 SMU71_Discrete_GraphicsLevel *graphic_level) in iceland_populate_single_graphic_level() argument
898 result = iceland_calculate_sclk_params(hwmgr, engine_clock, graphic_level); in iceland_populate_single_graphic_level()
903 &graphic_level->MinVddc); in iceland_populate_single_graphic_level()
908 graphic_level->SclkFrequency = engine_clock; in iceland_populate_single_graphic_level()
909 graphic_level->MinVddcPhases = 1; in iceland_populate_single_graphic_level()
915 &graphic_level->MinVddcPhases); in iceland_populate_single_graphic_level()
918 graphic_level->ActivityLevel = data->current_profile_setting.sclk_activity; in iceland_populate_single_graphic_level()
920 graphic_level->CcPwrDynRm = 0; in iceland_populate_single_graphic_level()
921 graphic_level->CcPwrDynRm1 = 0; in iceland_populate_single_graphic_level()
923 graphic_level->EnabledForActivity = 0; in iceland_populate_single_graphic_level()
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Dtonga_smumgr.c618 SMU72_Discrete_GraphicsLevel *graphic_level) in tonga_populate_single_graphic_level() argument
627 result = tonga_calculate_sclk_params(hwmgr, engine_clock, graphic_level); in tonga_populate_single_graphic_level()
637 &graphic_level->MinVoltage, &mvdd); in tonga_populate_single_graphic_level()
643 graphic_level->SclkFrequency = engine_clock; in tonga_populate_single_graphic_level()
645 graphic_level->ActivityLevel = data->current_profile_setting.sclk_activity; in tonga_populate_single_graphic_level()
647 graphic_level->CcPwrDynRm = 0; in tonga_populate_single_graphic_level()
648 graphic_level->CcPwrDynRm1 = 0; in tonga_populate_single_graphic_level()
650 graphic_level->EnabledForActivity = 0; in tonga_populate_single_graphic_level()
652 graphic_level->EnabledForThrottle = 1; in tonga_populate_single_graphic_level()
653 graphic_level->UpHyst = data->current_profile_setting.sclk_up_hyst; in tonga_populate_single_graphic_level()
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/linux-5.19.10/drivers/gpu/drm/radeon/
Dci_dpm.c3181 SMU7_Discrete_GraphicsLevel *graphic_level) in ci_populate_single_graphic_level() argument
3186 ret = ci_calculate_sclk_params(rdev, engine_clock, graphic_level); in ci_populate_single_graphic_level()
3192 engine_clock, &graphic_level->MinVddc); in ci_populate_single_graphic_level()
3196 graphic_level->SclkFrequency = engine_clock; in ci_populate_single_graphic_level()
3198 graphic_level->Flags = 0; in ci_populate_single_graphic_level()
3199 graphic_level->MinVddcPhases = 1; in ci_populate_single_graphic_level()
3205 &graphic_level->MinVddcPhases); in ci_populate_single_graphic_level()
3207 graphic_level->ActivityLevel = sclk_activity_level_t; in ci_populate_single_graphic_level()
3209 graphic_level->CcPwrDynRm = 0; in ci_populate_single_graphic_level()
3210 graphic_level->CcPwrDynRm1 = 0; in ci_populate_single_graphic_level()
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