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Searched refs:gated (Results 1 – 25 of 47) sorted by relevance

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/linux-5.19.10/drivers/gpu/drm/radeon/
Dvce_v2_0.c39 static void vce_v2_0_set_sw_cg(struct radeon_device *rdev, bool gated) in vce_v2_0_set_sw_cg() argument
43 if (gated) { in vce_v2_0_set_sw_cg()
74 static void vce_v2_0_set_dyn_cg(struct radeon_device *rdev, bool gated) in vce_v2_0_set_dyn_cg() argument
80 if (gated) { in vce_v2_0_set_dyn_cg()
99 if (gated) in vce_v2_0_set_dyn_cg()
/linux-5.19.10/sound/pci/hda/
Dhda_jack.c216 struct hda_jack_tbl *gated = in jack_detect_update() local
219 if (gated) { in jack_detect_update()
220 gated->jack_dirty = 1; in jack_detect_update()
221 jack_detect_update(codec, gated); in jack_detect_update()
386 struct hda_jack_tbl *gated = snd_hda_jack_tbl_new(codec, gated_nid, 0); in snd_hda_jack_set_gating_jack() local
392 if (!gated || !gating) in snd_hda_jack_set_gating_jack()
395 gated->gating_jack = gating_nid; in snd_hda_jack_set_gating_jack()
695 struct hda_jack_tbl *gated = in call_jack_callback() local
698 if (gated) { in call_jack_callback()
699 for (cb = gated->callback; cb; cb = cb->next) { in call_jack_callback()
[all …]
/linux-5.19.10/Documentation/devicetree/bindings/clock/
Dmaxim,max77686.txt11 (gated/ungated) over I2C. Clocks are defined as preprocessor macros in
16 (gated/ungated) over I2C. Clocks are defined as preprocessor macros in
20 (gated/ungated) over I2C. Clocks are defined as preprocessor macros in
Dmaxim,max9485.txt5 - MAX9485_MCLKOUT: A gated, buffered output of the input clock of 27 MHz
8 - MAX9485_CLKOUT[1,2]: Two gated outputs for MAX9485_CLKOUT
Dgpio-gate-clock.txt1 Binding for simple gpio gated clock.
Dst,stm32-rcc.txt21 between gated clocks and other clocks and an index specifying the clock to
37 Specifying gated clocks
Dfsl,sai-clock.yaml20 This is a composite of a gated clock and a divider clock.
Daltr_socfpga.txt13 can get gated.
/linux-5.19.10/drivers/gpu/drm/amd/amdgpu/
Dvce_v2_0.c310 static void vce_v2_0_set_sw_cg(struct amdgpu_device *adev, bool gated) in vce_v2_0_set_sw_cg() argument
314 if (gated) { in vce_v2_0_set_sw_cg()
345 static void vce_v2_0_set_dyn_cg(struct amdgpu_device *adev, bool gated) in vce_v2_0_set_dyn_cg() argument
356 if (gated) { in vce_v2_0_set_dyn_cg()
379 if(gated) in vce_v2_0_set_dyn_cg()
/linux-5.19.10/Documentation/devicetree/bindings/power/
Dapple,pmgr-pwrstate.yaml67 0 = power gated, 4 = clock gated, 15 = on.
/linux-5.19.10/arch/arm/boot/dts/
Dast2500-facebook-netbmc-common.dtsi14 * when reset type is set to default ("soc", gated by reset mask registers).
Drk3288-veyron-brain.dts27 /* This is gated by vcc_18 too */
/linux-5.19.10/Documentation/arm/sunxi/
Dclocks.rst11 A: The 24MHz oscillator allows gating to save power. Indeed, if gated
/linux-5.19.10/Documentation/devicetree/bindings/arm/msm/
Dqcom,idle-state.txt26 Retention: Retention is a low power state where the core is clock gated and
50 be flushed, system bus, clocks - lowered, and SoC main XO clock gated and
/linux-5.19.10/drivers/video/fbdev/
Dpxa168fb.h279 #define CFG_GATED_ENA(gated) ((gated) << 21) argument
/linux-5.19.10/Documentation/arm/samsung/
Dbootloader-interface.rst80 modules are power gated, except the TOP modules
/linux-5.19.10/Documentation/devicetree/bindings/mfd/
Dmaxim,max77686.yaml21 (gated/ungated) over I2C. The clock IDs are defined as preprocessor macros
Dmaxim,max77802.yaml22 (gated/ungated) over I2C. The clock IDs are defined as preprocessor macros
/linux-5.19.10/Documentation/hwmon/
Dpc87427.rst38 Fan rotation speeds are reported as 14-bit values from a gated clock
/linux-5.19.10/drivers/clk/bcm/
DKconfig33 bool "Broadcom BCM63xx gated clock support"
/linux-5.19.10/Documentation/devicetree/bindings/timer/
Darm,sp804.yaml15 free-running mode. The input clock is shared, but can be gated and prescaled
/linux-5.19.10/Documentation/mips/
Dingenic-tcu.rst19 different clocks (pclk, ext, rtc), gated, and reclocked, through their TCSR register.
/linux-5.19.10/Documentation/devicetree/bindings/memory-controllers/
Drockchip,rk3399-dmc.yaml100 self-refresh mode. The controller, pi, PHY and DRAM clock will be gated
313 self-refresh mode. The controller, pi, PHY and DRAM clock will be gated
332 sr-mc-gate-idle-dis-freq, the clock will not be gated when idle. See also
/linux-5.19.10/Documentation/ABI/testing/
Dsysfs-bus-iio-timer-stm32129 gated:
/linux-5.19.10/arch/arm/mach-tegra/
Dreset-handler.S277 wfi @ CPU should be power gated here

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