1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2 /* Copyright (c) 2019, Mellanox Technologies */ 3 4 #ifndef MLX5_IFC_DR_H 5 #define MLX5_IFC_DR_H 6 7 enum { 8 MLX5DR_STE_LU_TYPE_DONT_CARE = 0x0f, 9 }; 10 11 struct mlx5_ifc_ste_general_bits { 12 u8 entry_type[0x4]; 13 u8 reserved_at_4[0x4]; 14 u8 entry_sub_type[0x8]; 15 u8 byte_mask[0x10]; 16 17 u8 next_table_base_63_48[0x10]; 18 u8 next_lu_type[0x8]; 19 u8 next_table_base_39_32_size[0x8]; 20 21 u8 next_table_base_31_5_size[0x1b]; 22 u8 linear_hash_enable[0x1]; 23 u8 reserved_at_5c[0x2]; 24 u8 next_table_rank[0x2]; 25 26 u8 reserved_at_60[0xa0]; 27 u8 tag_value[0x60]; 28 u8 bit_mask[0x60]; 29 }; 30 31 struct mlx5_ifc_ste_sx_transmit_bits { 32 u8 entry_type[0x4]; 33 u8 reserved_at_4[0x4]; 34 u8 entry_sub_type[0x8]; 35 u8 byte_mask[0x10]; 36 37 u8 next_table_base_63_48[0x10]; 38 u8 next_lu_type[0x8]; 39 u8 next_table_base_39_32_size[0x8]; 40 41 u8 next_table_base_31_5_size[0x1b]; 42 u8 linear_hash_enable[0x1]; 43 u8 reserved_at_5c[0x2]; 44 u8 next_table_rank[0x2]; 45 46 u8 sx_wire[0x1]; 47 u8 sx_func_lb[0x1]; 48 u8 sx_sniffer[0x1]; 49 u8 sx_wire_enable[0x1]; 50 u8 sx_func_lb_enable[0x1]; 51 u8 sx_sniffer_enable[0x1]; 52 u8 action_type[0x3]; 53 u8 reserved_at_69[0x1]; 54 u8 action_description[0x6]; 55 u8 gvmi[0x10]; 56 57 u8 encap_pointer_vlan_data[0x20]; 58 59 u8 loopback_syndome_en[0x8]; 60 u8 loopback_syndome[0x8]; 61 u8 counter_trigger[0x10]; 62 63 u8 miss_address_63_48[0x10]; 64 u8 counter_trigger_23_16[0x8]; 65 u8 miss_address_39_32[0x8]; 66 67 u8 miss_address_31_6[0x1a]; 68 u8 learning_point[0x1]; 69 u8 go_back[0x1]; 70 u8 match_polarity[0x1]; 71 u8 mask_mode[0x1]; 72 u8 miss_rank[0x2]; 73 }; 74 75 struct mlx5_ifc_ste_rx_steering_mult_bits { 76 u8 entry_type[0x4]; 77 u8 reserved_at_4[0x4]; 78 u8 entry_sub_type[0x8]; 79 u8 byte_mask[0x10]; 80 81 u8 next_table_base_63_48[0x10]; 82 u8 next_lu_type[0x8]; 83 u8 next_table_base_39_32_size[0x8]; 84 85 u8 next_table_base_31_5_size[0x1b]; 86 u8 linear_hash_enable[0x1]; 87 u8 reserved_at_[0x2]; 88 u8 next_table_rank[0x2]; 89 90 u8 member_count[0x10]; 91 u8 gvmi[0x10]; 92 93 u8 qp_list_pointer[0x20]; 94 95 u8 reserved_at_a0[0x1]; 96 u8 tunneling_action[0x3]; 97 u8 action_description[0x4]; 98 u8 reserved_at_a8[0x8]; 99 u8 counter_trigger_15_0[0x10]; 100 101 u8 miss_address_63_48[0x10]; 102 u8 counter_trigger_23_16[0x08]; 103 u8 miss_address_39_32[0x8]; 104 105 u8 miss_address_31_6[0x1a]; 106 u8 learning_point[0x1]; 107 u8 fail_on_error[0x1]; 108 u8 match_polarity[0x1]; 109 u8 mask_mode[0x1]; 110 u8 miss_rank[0x2]; 111 }; 112 113 struct mlx5_ifc_ste_modify_packet_bits { 114 u8 entry_type[0x4]; 115 u8 reserved_at_4[0x4]; 116 u8 entry_sub_type[0x8]; 117 u8 byte_mask[0x10]; 118 119 u8 next_table_base_63_48[0x10]; 120 u8 next_lu_type[0x8]; 121 u8 next_table_base_39_32_size[0x8]; 122 123 u8 next_table_base_31_5_size[0x1b]; 124 u8 linear_hash_enable[0x1]; 125 u8 reserved_at_[0x2]; 126 u8 next_table_rank[0x2]; 127 128 u8 number_of_re_write_actions[0x10]; 129 u8 gvmi[0x10]; 130 131 u8 header_re_write_actions_pointer[0x20]; 132 133 u8 reserved_at_a0[0x1]; 134 u8 tunneling_action[0x3]; 135 u8 action_description[0x4]; 136 u8 reserved_at_a8[0x8]; 137 u8 counter_trigger_15_0[0x10]; 138 139 u8 miss_address_63_48[0x10]; 140 u8 counter_trigger_23_16[0x08]; 141 u8 miss_address_39_32[0x8]; 142 143 u8 miss_address_31_6[0x1a]; 144 u8 learning_point[0x1]; 145 u8 fail_on_error[0x1]; 146 u8 match_polarity[0x1]; 147 u8 mask_mode[0x1]; 148 u8 miss_rank[0x2]; 149 }; 150 151 struct mlx5_ifc_ste_eth_l2_src_bits { 152 u8 smac_47_16[0x20]; 153 154 u8 smac_15_0[0x10]; 155 u8 l3_ethertype[0x10]; 156 157 u8 qp_type[0x2]; 158 u8 ethertype_filter[0x1]; 159 u8 reserved_at_43[0x1]; 160 u8 sx_sniffer[0x1]; 161 u8 force_lb[0x1]; 162 u8 functional_lb[0x1]; 163 u8 port[0x1]; 164 u8 reserved_at_48[0x4]; 165 u8 first_priority[0x3]; 166 u8 first_cfi[0x1]; 167 u8 first_vlan_qualifier[0x2]; 168 u8 reserved_at_52[0x2]; 169 u8 first_vlan_id[0xc]; 170 171 u8 ip_fragmented[0x1]; 172 u8 tcp_syn[0x1]; 173 u8 encp_type[0x2]; 174 u8 l3_type[0x2]; 175 u8 l4_type[0x2]; 176 u8 reserved_at_68[0x4]; 177 u8 second_priority[0x3]; 178 u8 second_cfi[0x1]; 179 u8 second_vlan_qualifier[0x2]; 180 u8 reserved_at_72[0x2]; 181 u8 second_vlan_id[0xc]; 182 }; 183 184 struct mlx5_ifc_ste_eth_l2_dst_bits { 185 u8 dmac_47_16[0x20]; 186 187 u8 dmac_15_0[0x10]; 188 u8 l3_ethertype[0x10]; 189 190 u8 qp_type[0x2]; 191 u8 ethertype_filter[0x1]; 192 u8 reserved_at_43[0x1]; 193 u8 sx_sniffer[0x1]; 194 u8 force_lb[0x1]; 195 u8 functional_lb[0x1]; 196 u8 port[0x1]; 197 u8 reserved_at_48[0x4]; 198 u8 first_priority[0x3]; 199 u8 first_cfi[0x1]; 200 u8 first_vlan_qualifier[0x2]; 201 u8 reserved_at_52[0x2]; 202 u8 first_vlan_id[0xc]; 203 204 u8 ip_fragmented[0x1]; 205 u8 tcp_syn[0x1]; 206 u8 encp_type[0x2]; 207 u8 l3_type[0x2]; 208 u8 l4_type[0x2]; 209 u8 reserved_at_68[0x4]; 210 u8 second_priority[0x3]; 211 u8 second_cfi[0x1]; 212 u8 second_vlan_qualifier[0x2]; 213 u8 reserved_at_72[0x2]; 214 u8 second_vlan_id[0xc]; 215 }; 216 217 struct mlx5_ifc_ste_eth_l2_src_dst_bits { 218 u8 dmac_47_16[0x20]; 219 220 u8 dmac_15_0[0x10]; 221 u8 smac_47_32[0x10]; 222 223 u8 smac_31_0[0x20]; 224 225 u8 sx_sniffer[0x1]; 226 u8 force_lb[0x1]; 227 u8 functional_lb[0x1]; 228 u8 port[0x1]; 229 u8 l3_type[0x2]; 230 u8 reserved_at_66[0x6]; 231 u8 first_priority[0x3]; 232 u8 first_cfi[0x1]; 233 u8 first_vlan_qualifier[0x2]; 234 u8 reserved_at_72[0x2]; 235 u8 first_vlan_id[0xc]; 236 }; 237 238 struct mlx5_ifc_ste_eth_l3_ipv4_5_tuple_bits { 239 u8 destination_address[0x20]; 240 241 u8 source_address[0x20]; 242 243 u8 source_port[0x10]; 244 u8 destination_port[0x10]; 245 246 u8 fragmented[0x1]; 247 u8 first_fragment[0x1]; 248 u8 reserved_at_62[0x2]; 249 u8 reserved_at_64[0x1]; 250 u8 ecn[0x2]; 251 u8 tcp_ns[0x1]; 252 u8 tcp_cwr[0x1]; 253 u8 tcp_ece[0x1]; 254 u8 tcp_urg[0x1]; 255 u8 tcp_ack[0x1]; 256 u8 tcp_psh[0x1]; 257 u8 tcp_rst[0x1]; 258 u8 tcp_syn[0x1]; 259 u8 tcp_fin[0x1]; 260 u8 dscp[0x6]; 261 u8 reserved_at_76[0x2]; 262 u8 protocol[0x8]; 263 }; 264 265 struct mlx5_ifc_ste_eth_l3_ipv6_dst_bits { 266 u8 dst_ip_127_96[0x20]; 267 268 u8 dst_ip_95_64[0x20]; 269 270 u8 dst_ip_63_32[0x20]; 271 272 u8 dst_ip_31_0[0x20]; 273 }; 274 275 struct mlx5_ifc_ste_eth_l2_tnl_bits { 276 u8 dmac_47_16[0x20]; 277 278 u8 dmac_15_0[0x10]; 279 u8 l3_ethertype[0x10]; 280 281 u8 l2_tunneling_network_id[0x20]; 282 283 u8 ip_fragmented[0x1]; 284 u8 tcp_syn[0x1]; 285 u8 encp_type[0x2]; 286 u8 l3_type[0x2]; 287 u8 l4_type[0x2]; 288 u8 first_priority[0x3]; 289 u8 first_cfi[0x1]; 290 u8 reserved_at_6c[0x3]; 291 u8 gre_key_flag[0x1]; 292 u8 first_vlan_qualifier[0x2]; 293 u8 reserved_at_72[0x2]; 294 u8 first_vlan_id[0xc]; 295 }; 296 297 struct mlx5_ifc_ste_eth_l3_ipv6_src_bits { 298 u8 src_ip_127_96[0x20]; 299 300 u8 src_ip_95_64[0x20]; 301 302 u8 src_ip_63_32[0x20]; 303 304 u8 src_ip_31_0[0x20]; 305 }; 306 307 struct mlx5_ifc_ste_eth_l3_ipv4_misc_bits { 308 u8 version[0x4]; 309 u8 ihl[0x4]; 310 u8 reserved_at_8[0x8]; 311 u8 total_length[0x10]; 312 313 u8 identification[0x10]; 314 u8 flags[0x3]; 315 u8 fragment_offset[0xd]; 316 317 u8 time_to_live[0x8]; 318 u8 reserved_at_48[0x8]; 319 u8 checksum[0x10]; 320 321 u8 reserved_at_60[0x20]; 322 }; 323 324 struct mlx5_ifc_ste_eth_l4_bits { 325 u8 fragmented[0x1]; 326 u8 first_fragment[0x1]; 327 u8 reserved_at_2[0x6]; 328 u8 protocol[0x8]; 329 u8 dst_port[0x10]; 330 331 u8 ipv6_version[0x4]; 332 u8 reserved_at_24[0x1]; 333 u8 ecn[0x2]; 334 u8 tcp_ns[0x1]; 335 u8 tcp_cwr[0x1]; 336 u8 tcp_ece[0x1]; 337 u8 tcp_urg[0x1]; 338 u8 tcp_ack[0x1]; 339 u8 tcp_psh[0x1]; 340 u8 tcp_rst[0x1]; 341 u8 tcp_syn[0x1]; 342 u8 tcp_fin[0x1]; 343 u8 src_port[0x10]; 344 345 u8 ipv6_payload_length[0x10]; 346 u8 ipv6_hop_limit[0x8]; 347 u8 dscp[0x6]; 348 u8 reserved_at_5e[0x2]; 349 350 u8 tcp_data_offset[0x4]; 351 u8 reserved_at_64[0x8]; 352 u8 flow_label[0x14]; 353 }; 354 355 struct mlx5_ifc_ste_eth_l4_misc_bits { 356 u8 checksum[0x10]; 357 u8 length[0x10]; 358 359 u8 seq_num[0x20]; 360 361 u8 ack_num[0x20]; 362 363 u8 urgent_pointer[0x10]; 364 u8 window_size[0x10]; 365 }; 366 367 struct mlx5_ifc_ste_mpls_bits { 368 u8 mpls0_label[0x14]; 369 u8 mpls0_exp[0x3]; 370 u8 mpls0_s_bos[0x1]; 371 u8 mpls0_ttl[0x8]; 372 373 u8 mpls1_label[0x20]; 374 375 u8 mpls2_label[0x20]; 376 377 u8 reserved_at_60[0x16]; 378 u8 mpls4_s_bit[0x1]; 379 u8 mpls4_qualifier[0x1]; 380 u8 mpls3_s_bit[0x1]; 381 u8 mpls3_qualifier[0x1]; 382 u8 mpls2_s_bit[0x1]; 383 u8 mpls2_qualifier[0x1]; 384 u8 mpls1_s_bit[0x1]; 385 u8 mpls1_qualifier[0x1]; 386 u8 mpls0_s_bit[0x1]; 387 u8 mpls0_qualifier[0x1]; 388 }; 389 390 struct mlx5_ifc_ste_register_0_bits { 391 u8 register_0_h[0x20]; 392 393 u8 register_0_l[0x20]; 394 395 u8 register_1_h[0x20]; 396 397 u8 register_1_l[0x20]; 398 }; 399 400 struct mlx5_ifc_ste_register_1_bits { 401 u8 register_2_h[0x20]; 402 403 u8 register_2_l[0x20]; 404 405 u8 register_3_h[0x20]; 406 407 u8 register_3_l[0x20]; 408 }; 409 410 struct mlx5_ifc_ste_gre_bits { 411 u8 gre_c_present[0x1]; 412 u8 reserved_at_30[0x1]; 413 u8 gre_k_present[0x1]; 414 u8 gre_s_present[0x1]; 415 u8 strict_src_route[0x1]; 416 u8 recur[0x3]; 417 u8 flags[0x5]; 418 u8 version[0x3]; 419 u8 gre_protocol[0x10]; 420 421 u8 checksum[0x10]; 422 u8 offset[0x10]; 423 424 u8 gre_key_h[0x18]; 425 u8 gre_key_l[0x8]; 426 427 u8 seq_num[0x20]; 428 }; 429 430 struct mlx5_ifc_ste_flex_parser_0_bits { 431 u8 flex_parser_3[0x20]; 432 433 u8 flex_parser_2[0x20]; 434 435 u8 flex_parser_1[0x20]; 436 437 u8 flex_parser_0[0x20]; 438 }; 439 440 struct mlx5_ifc_ste_flex_parser_1_bits { 441 u8 flex_parser_7[0x20]; 442 443 u8 flex_parser_6[0x20]; 444 445 u8 flex_parser_5[0x20]; 446 447 u8 flex_parser_4[0x20]; 448 }; 449 450 struct mlx5_ifc_ste_flex_parser_ok_bits { 451 u8 flex_parser_3[0x20]; 452 u8 flex_parser_2[0x20]; 453 u8 flex_parsers_ok[0x8]; 454 u8 reserved_at_48[0x18]; 455 u8 flex_parser_0[0x20]; 456 }; 457 458 struct mlx5_ifc_ste_flex_parser_tnl_bits { 459 u8 flex_parser_tunneling_header_63_32[0x20]; 460 461 u8 flex_parser_tunneling_header_31_0[0x20]; 462 463 u8 reserved_at_40[0x40]; 464 }; 465 466 struct mlx5_ifc_ste_flex_parser_tnl_vxlan_gpe_bits { 467 u8 outer_vxlan_gpe_flags[0x8]; 468 u8 reserved_at_8[0x10]; 469 u8 outer_vxlan_gpe_next_protocol[0x8]; 470 471 u8 outer_vxlan_gpe_vni[0x18]; 472 u8 reserved_at_38[0x8]; 473 474 u8 reserved_at_40[0x40]; 475 }; 476 477 struct mlx5_ifc_ste_flex_parser_tnl_geneve_bits { 478 u8 reserved_at_0[0x2]; 479 u8 geneve_opt_len[0x6]; 480 u8 geneve_oam[0x1]; 481 u8 reserved_at_9[0x7]; 482 u8 geneve_protocol_type[0x10]; 483 484 u8 geneve_vni[0x18]; 485 u8 reserved_at_38[0x8]; 486 487 u8 reserved_at_40[0x40]; 488 }; 489 490 struct mlx5_ifc_ste_flex_parser_tnl_gtpu_bits { 491 u8 reserved_at_0[0x5]; 492 u8 gtpu_msg_flags[0x3]; 493 u8 gtpu_msg_type[0x8]; 494 u8 reserved_at_10[0x10]; 495 496 u8 gtpu_teid[0x20]; 497 498 u8 reserved_at_40[0x40]; 499 }; 500 501 struct mlx5_ifc_ste_tunnel_header_bits { 502 u8 tunnel_header_0[0x20]; 503 504 u8 tunnel_header_1[0x20]; 505 506 u8 reserved_at_40[0x40]; 507 }; 508 509 struct mlx5_ifc_ste_general_purpose_bits { 510 u8 general_purpose_lookup_field[0x20]; 511 512 u8 reserved_at_20[0x20]; 513 514 u8 reserved_at_40[0x20]; 515 516 u8 reserved_at_60[0x20]; 517 }; 518 519 struct mlx5_ifc_ste_src_gvmi_qp_bits { 520 u8 loopback_syndrome[0x8]; 521 u8 reserved_at_8[0x8]; 522 u8 source_gvmi[0x10]; 523 524 u8 reserved_at_20[0x5]; 525 u8 force_lb[0x1]; 526 u8 functional_lb[0x1]; 527 u8 source_is_requestor[0x1]; 528 u8 source_qp[0x18]; 529 530 u8 reserved_at_40[0x20]; 531 532 u8 reserved_at_60[0x20]; 533 }; 534 535 struct mlx5_ifc_l2_hdr_bits { 536 u8 dmac_47_16[0x20]; 537 538 u8 dmac_15_0[0x10]; 539 u8 smac_47_32[0x10]; 540 541 u8 smac_31_0[0x20]; 542 543 u8 ethertype[0x10]; 544 u8 vlan_type[0x10]; 545 546 u8 vlan[0x10]; 547 u8 reserved_at_90[0x10]; 548 }; 549 550 /* Both HW set and HW add share the same HW format with different opcodes */ 551 struct mlx5_ifc_dr_action_hw_set_bits { 552 u8 opcode[0x8]; 553 u8 destination_field_code[0x8]; 554 u8 reserved_at_10[0x2]; 555 u8 destination_left_shifter[0x6]; 556 u8 reserved_at_18[0x3]; 557 u8 destination_length[0x5]; 558 559 u8 inline_data[0x20]; 560 }; 561 562 struct mlx5_ifc_dr_action_hw_copy_bits { 563 u8 opcode[0x8]; 564 u8 destination_field_code[0x8]; 565 u8 reserved_at_10[0x2]; 566 u8 destination_left_shifter[0x6]; 567 u8 reserved_at_18[0x2]; 568 u8 destination_length[0x6]; 569 570 u8 reserved_at_20[0x8]; 571 u8 source_field_code[0x8]; 572 u8 reserved_at_30[0x2]; 573 u8 source_left_shifter[0x6]; 574 u8 reserved_at_38[0x8]; 575 }; 576 577 #endif /* MLX5_IFC_DR_H */ 578