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Searched refs:fixed_clks (Results 1 – 11 of 11) sorted by relevance

/linux-5.19.10/drivers/clk/mediatek/
Dclk-mt8516.c22 static const struct mtk_fixed_clk fixed_clks[] __initconst = { variable
692 mtk_clk_register_fixed_clks(fixed_clks, ARRAY_SIZE(fixed_clks), in mtk_topckgen_init()
Dclk-mt8167.c23 static const struct mtk_fixed_clk fixed_clks[] __initconst = { variable
938 mtk_clk_register_fixed_clks(fixed_clks, ARRAY_SIZE(fixed_clks), in mtk_topckgen_init()
Dclk-mt6765.c76 static const struct mtk_fixed_clk fixed_clks[] = { variable
825 mtk_clk_register_fixed_clks(fixed_clks, ARRAY_SIZE(fixed_clks), in clk_mt6765_top_probe()
Dclk-mt8173.c27 static const struct mtk_fixed_clk fixed_clks[] __initconst = { variable
852 mtk_clk_register_fixed_clks(fixed_clks, ARRAY_SIZE(fixed_clks), clk_data); in mtk_topckgen_init()
/linux-5.19.10/drivers/clk/samsung/
Dclk.c357 if (cmu->fixed_clks) in samsung_cmu_register_one()
358 samsung_clk_register_fixed_rate(ctx, cmu->fixed_clks, in samsung_cmu_register_one()
Dclk-exynos850.c458 .fixed_clks = apm_fixed_clks,
561 .fixed_clks = cmgp_fixed_clks,
Dclk.h318 const struct samsung_fixed_rate_clock *fixed_clks; member
Dclk-fsd.c668 .fixed_clks = peric_fixed_clks,
967 .fixed_clks = fsys0_fixed_clks,
1139 .fixed_clks = fsys1_fixed_clks,
Dclk-exynos7.c966 .fixed_clks = fixed_rate_clks_fsys0,
1095 .fixed_clks = fixed_rate_clks_fsys1,
Dclk-exynos5433.c797 .fixed_clks = top_fixed_clks,
2337 .fixed_clks = fsys_fixed_clks,
2886 .fixed_clks = disp_fixed_clks,
3058 .fixed_clks = aud_fixed_clks,
5066 .fixed_clks = cam0_fixed_clks,
5441 .fixed_clks = cam1_fixed_clks,
5624 if (info->fixed_clks) in exynos5433_cmu_probe()
5625 samsung_clk_register_fixed_rate(ctx, info->fixed_clks, in exynos5433_cmu_probe()
Dclk-exynos5260.c1827 .fixed_clks = fixed_rate_clks,