| /linux-5.19.10/drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_fence.c | 102 struct amdgpu_fence_driver *drv = &ring->fence_drv; in amdgpu_fence_write()
118 struct amdgpu_fence_driver *drv = &ring->fence_drv; in amdgpu_fence_read()
162 seq = ++ring->fence_drv.sync_seq; in amdgpu_fence_emit()
169 &ring->fence_drv.lock, in amdgpu_fence_emit()
173 &ring->fence_drv.lock, in amdgpu_fence_emit()
177 amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr, in amdgpu_fence_emit()
180 ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask]; in amdgpu_fence_emit()
226 seq = ++ring->fence_drv.sync_seq; in amdgpu_fence_emit_polling()
228 seq - ring->fence_drv.num_fences_mask, in amdgpu_fence_emit_polling()
233 amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr, in amdgpu_fence_emit_polling()
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| D | mes_v10_1.c | 108 r = amdgpu_fence_wait_polling(ring, ring->fence_drv.sync_seq, in mes_v10_1_submit_pkt_and_poll_completion()
170 mes->ring.fence_drv.gpu_addr; in mes_v10_1_add_hw_queue()
172 ++mes->ring.fence_drv.sync_seq; in mes_v10_1_add_hw_queue()
193 mes->ring.fence_drv.gpu_addr; in mes_v10_1_remove_hw_queue()
195 ++mes->ring.fence_drv.sync_seq; in mes_v10_1_remove_hw_queue()
231 mes->ring.fence_drv.gpu_addr; in mes_v10_1_unmap_legacy_queue()
233 ++mes->ring.fence_drv.sync_seq; in mes_v10_1_unmap_legacy_queue()
262 mes->ring.fence_drv.gpu_addr; in mes_v10_1_query_sched_status()
264 ++mes->ring.fence_drv.sync_seq; in mes_v10_1_query_sched_status()
317 mes->ring.fence_drv.gpu_addr; in mes_v10_1_set_hw_resources()
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| D | mes_v11_0.c | 107 r = amdgpu_fence_wait_polling(ring, ring->fence_drv.sync_seq, in mes_v11_0_submit_pkt_and_poll_completion()
170 mes->ring.fence_drv.gpu_addr; in mes_v11_0_add_hw_queue()
172 ++mes->ring.fence_drv.sync_seq; in mes_v11_0_add_hw_queue()
193 mes->ring.fence_drv.gpu_addr; in mes_v11_0_remove_hw_queue()
195 ++mes->ring.fence_drv.sync_seq; in mes_v11_0_remove_hw_queue()
231 mes->ring.fence_drv.gpu_addr; in mes_v11_0_unmap_legacy_queue()
233 ++mes->ring.fence_drv.sync_seq; in mes_v11_0_unmap_legacy_queue()
262 mes->ring.fence_drv.gpu_addr; in mes_v11_0_query_sched_status()
264 ++mes->ring.fence_drv.sync_seq; in mes_v11_0_query_sched_status()
317 mes->ring.fence_drv.gpu_addr; in mes_v11_0_set_hw_resources()
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| D | amdgpu_job.c | 61 job->base.sched->name, atomic_read(&ring->fence_drv.last_seq), in amdgpu_job_timedout()
62 ring->fence_drv.sync_seq); in amdgpu_job_timedout()
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| D | amdgpu_debugfs.c | 1433 struct amdgpu_fence_driver *drv = &ring->fence_drv; in amdgpu_ib_preempt_fences_swap()
1436 last_seq = atomic_read(&ring->fence_drv.last_seq); in amdgpu_ib_preempt_fences_swap()
1437 sync_seq = ring->fence_drv.sync_seq; in amdgpu_ib_preempt_fences_swap()
1494 struct amdgpu_fence_driver *drv = &ring->fence_drv; in amdgpu_ib_preempt_mark_partial_job()
1547 length = ring->fence_drv.num_fences_mask + 1; in amdgpu_debugfs_ib_preempt()
1571 if (atomic_read(&ring->fence_drv.last_seq) != in amdgpu_debugfs_ib_preempt()
1572 ring->fence_drv.sync_seq) { in amdgpu_debugfs_ib_preempt()
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| D | uvd_v6_0.c | 1088 uint32_t seq = ring->fence_drv.sync_seq; in uvd_v6_0_ring_emit_pipeline_sync()
1089 uint64_t addr = ring->fence_drv.gpu_addr; in uvd_v6_0_ring_emit_pipeline_sync()
1117 uint32_t seq = ring->fence_drv.sync_seq; in uvd_v6_0_enc_ring_emit_pipeline_sync()
1118 uint64_t addr = ring->fence_drv.gpu_addr; in uvd_v6_0_enc_ring_emit_pipeline_sync()
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| D | si_dma.c | 425 uint32_t seq = ring->fence_drv.sync_seq; in si_dma_ring_emit_pipeline_sync()
426 uint64_t addr = ring->fence_drv.gpu_addr; in si_dma_ring_emit_pipeline_sync()
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| D | vce_v3_0.c | 890 uint32_t seq = ring->fence_drv.sync_seq; in vce_v3_0_emit_pipeline_sync()
891 uint64_t addr = ring->fence_drv.gpu_addr; in vce_v3_0_emit_pipeline_sync()
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| D | sdma_v2_4.c | 776 uint32_t seq = ring->fence_drv.sync_seq; in sdma_v2_4_ring_emit_pipeline_sync()
777 uint64_t addr = ring->fence_drv.gpu_addr; in sdma_v2_4_ring_emit_pipeline_sync()
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| D | amdgpu_ring.h | 227 struct amdgpu_fence_driver fence_drv; member
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| D | cik_sdma.c | 837 uint32_t seq = ring->fence_drv.sync_seq; in cik_sdma_ring_emit_pipeline_sync()
838 uint64_t addr = ring->fence_drv.gpu_addr; in cik_sdma_ring_emit_pipeline_sync()
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| D | sdma_v3_0.c | 1047 uint32_t seq = ring->fence_drv.sync_seq; in sdma_v3_0_ring_emit_pipeline_sync()
1048 uint64_t addr = ring->fence_drv.gpu_addr; in sdma_v3_0_ring_emit_pipeline_sync()
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| D | sdma_v6_0.c | 1184 uint32_t seq = ring->fence_drv.sync_seq; in sdma_v6_0_ring_emit_pipeline_sync()
1185 uint64_t addr = ring->fence_drv.gpu_addr; in sdma_v6_0_ring_emit_pipeline_sync()
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| /linux-5.19.10/drivers/gpu/drm/radeon/ |
| D | radeon_fence.c | 69 struct radeon_fence_driver *drv = &rdev->fence_drv[ring]; in radeon_fence_write()
90 struct radeon_fence_driver *drv = &rdev->fence_drv[ring]; in radeon_fence_read()
120 &rdev->fence_drv[ring].lockup_work, in radeon_fence_schedule_check()
146 (*fence)->seq = seq = ++rdev->fence_drv[ring].sync_seq[ring]; in radeon_fence_emit()
177 seq = atomic64_read(&fence->rdev->fence_drv[fence->ring].last_seq); in radeon_fence_check_signaled()
224 last_seq = atomic64_read(&rdev->fence_drv[ring].last_seq); in radeon_fence_activity()
226 last_emitted = rdev->fence_drv[ring].sync_seq[ring]; in radeon_fence_activity()
251 } while (atomic64_xchg(&rdev->fence_drv[ring].last_seq, seq) > seq); in radeon_fence_activity()
269 struct radeon_fence_driver *fence_drv; in radeon_fence_check_lockup() local
273 fence_drv = container_of(work, struct radeon_fence_driver, in radeon_fence_check_lockup()
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| D | uvd_v2_2.c | 43 uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr; in uvd_v2_2_fence_emit()
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| D | evergreen_dma.c | 44 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in evergreen_dma_fence_ring_emit()
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| D | uvd_v1_0.c | 85 uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr; in uvd_v1_0_fence_emit()
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| D | r600_dma.c | 290 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in r600_dma_fence_ring_emit()
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| D | radeon_vce.c | 738 uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr; in radeon_vce_fence_emit()
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| /linux-5.19.10/drivers/gpu/drm/virtio/ |
| D | virtgpu_fence.c | 79 struct virtio_gpu_fence_driver *drv = &vgdev->fence_drv; in virtio_gpu_fence_alloc()
105 struct virtio_gpu_fence_driver *drv = &vgdev->fence_drv; in virtio_gpu_fence_emit()
130 struct virtio_gpu_fence_driver *drv = &vgdev->fence_drv; in virtio_gpu_fence_event_process()
135 atomic64_set(&vgdev->fence_drv.last_fence_id, fence_id); in virtio_gpu_fence_event_process()
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| D | virtgpu_debugfs.c | 75 (u64)atomic64_read(&vgdev->fence_drv.last_fence_id), in virtio_gpu_debugfs_irq_info()
76 vgdev->fence_drv.current_fence_id); in virtio_gpu_debugfs_irq_info()
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| D | virtgpu_kms.c | 147 vgdev->fence_drv.context = dma_fence_context_alloc(1); in virtio_gpu_init()
148 spin_lock_init(&vgdev->fence_drv.lock); in virtio_gpu_init()
149 INIT_LIST_HEAD(&vgdev->fence_drv.fences); in virtio_gpu_init()
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| D | virtgpu_ioctl.c | 135 fence_ctx = vgdev->fence_drv.context; in virtio_gpu_execbuffer_ioctl()
171 if (!dma_fence_match_context(in_fence, vgdev->fence_drv.context)) in virtio_gpu_execbuffer_ioctl()
347 fence = virtio_gpu_fence_alloc(vgdev, vgdev->fence_drv.context, 0); in virtio_gpu_resource_create_ioctl()
426 fence = virtio_gpu_fence_alloc(vgdev, vgdev->fence_drv.context, 0); in virtio_gpu_transfer_from_host_ioctl()
486 fence = virtio_gpu_fence_alloc(vgdev, vgdev->fence_drv.context, in virtio_gpu_transfer_to_host_ioctl()
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| D | virtgpu_drv.h | 238 struct virtio_gpu_fence_driver fence_drv; member
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| D | virtgpu_plane.c | 259 vgfb->fence = virtio_gpu_fence_alloc(vgdev, vgdev->fence_drv.context, in virtio_gpu_plane_prepare_fb()
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