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Searched refs:engine_mask (Results 1 – 19 of 19) sorted by relevance

/linux-5.19.10/drivers/gpu/drm/i915/gt/
Dintel_reset.c168 intel_engine_mask_t engine_mask, in i915_do_reset() argument
197 intel_engine_mask_t engine_mask, in g33_do_reset() argument
207 intel_engine_mask_t engine_mask, in g4x_do_reset() argument
243 static int ilk_do_reset(struct intel_gt *gt, intel_engine_mask_t engine_mask, in ilk_do_reset() argument
304 intel_engine_mask_t engine_mask, in __gen6_reset_engines() argument
310 if (engine_mask == ALL_ENGINES) { in __gen6_reset_engines()
316 for_each_engine_masked(engine, gt, engine_mask, tmp) { in __gen6_reset_engines()
325 intel_engine_mask_t engine_mask, in gen6_reset_engines() argument
332 ret = __gen6_reset_engines(gt, engine_mask, retry); in gen6_reset_engines()
505 intel_engine_mask_t engine_mask, in __gen11_reset_engines() argument
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Dintel_reset.h26 intel_engine_mask_t engine_mask,
56 int __intel_gt_reset(struct intel_gt *gt, intel_engine_mask_t engine_mask);
Dintel_breadcrumbs_types.h49 intel_engine_mask_t engine_mask; member
Dintel_engine_cs.c620 info->engine_mask &= ~BIT(_CCS(i)); in engine_mask_apply_compute_fuses()
646 info->engine_mask = INTEL_INFO(i915)->platform_engine_mask; in init_engine_mask()
649 return info->engine_mask; in init_engine_mask()
678 info->engine_mask &= ~BIT(_VCS(i)); in init_engine_mask()
698 info->engine_mask &= ~BIT(_VECS(i)); in init_engine_mask()
708 return info->engine_mask; in init_engine_mask()
763 const unsigned int engine_mask = init_engine_mask(gt); in intel_engines_init_mmio() local
769 drm_WARN_ON(&i915->drm, engine_mask == 0); in intel_engines_init_mmio()
770 drm_WARN_ON(&i915->drm, engine_mask & in intel_engines_init_mmio()
800 if (drm_WARN_ON(&i915->drm, mask != engine_mask)) in intel_engines_init_mmio()
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Dintel_gt_types.h217 intel_engine_mask_t engine_mask; member
Dintel_gt.h71 intel_engine_mask_t engine_mask);
Dintel_gt.c290 intel_engine_mask_t engine_mask) in intel_gt_clear_error_registers() argument
327 for_each_engine_masked(engine, gt, engine_mask, id) in intel_gt_clear_error_registers()
1137 drm_printf(p, "available engines: %x\n", info->engine_mask); in intel_gt_info_print()
/linux-5.19.10/drivers/gpu/drm/i915/gvt/
Dscheduler.h150 intel_engine_mask_t engine_mask);
155 intel_engine_mask_t engine_mask,
169 intel_engine_mask_t engine_mask);
Dexeclist.c523 intel_engine_mask_t engine_mask) in clean_execlist() argument
529 for_each_engine_masked(engine, vgpu->gvt->gt, engine_mask, tmp) { in clean_execlist()
537 intel_engine_mask_t engine_mask) in reset_execlist() argument
542 for_each_engine_masked(engine, vgpu->gvt->gt, engine_mask, tmp) in reset_execlist()
547 intel_engine_mask_t engine_mask) in init_execlist() argument
549 reset_execlist(vgpu, engine_mask); in init_execlist()
Dvgpu.c531 intel_engine_mask_t engine_mask) in intel_gvt_reset_vgpu_locked() argument
535 intel_engine_mask_t resetting_eng = dmlr ? ALL_ENGINES : engine_mask; in intel_gvt_reset_vgpu_locked()
539 vgpu->id, dmlr, engine_mask); in intel_gvt_reset_vgpu_locked()
556 if (engine_mask == ALL_ENGINES || dmlr) { in intel_gvt_reset_vgpu_locked()
558 if (engine_mask == ALL_ENGINES) in intel_gvt_reset_vgpu_locked()
Dgvt.h143 int (*init)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask);
144 void (*clean)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask);
145 void (*reset)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask);
503 intel_engine_mask_t engine_mask);
Dscheduler.c1047 intel_engine_mask_t engine_mask) in intel_vgpu_clean_workloads() argument
1055 for_each_engine_masked(engine, vgpu->gvt->gt, engine_mask, tmp) { in intel_vgpu_clean_workloads()
1342 intel_engine_mask_t engine_mask) in intel_vgpu_reset_submission() argument
1349 intel_vgpu_clean_workloads(vgpu, engine_mask); in intel_vgpu_reset_submission()
1350 s->ops->reset(vgpu, engine_mask); in intel_vgpu_reset_submission()
1466 intel_engine_mask_t engine_mask, in intel_vgpu_select_submission_ops() argument
1481 interface == 0 && engine_mask != ALL_ENGINES)) in intel_vgpu_select_submission_ops()
1485 s->ops->clean(vgpu, engine_mask); in intel_vgpu_select_submission_ops()
1495 ret = ops[interface]->init(vgpu, engine_mask); in intel_vgpu_select_submission_ops()
Dhandlers.c308 intel_engine_mask_t engine_mask = 0; in gdrst_mmio_write() local
316 engine_mask = ALL_ENGINES; in gdrst_mmio_write()
320 engine_mask |= BIT(RCS0); in gdrst_mmio_write()
324 engine_mask |= BIT(VCS0); in gdrst_mmio_write()
328 engine_mask |= BIT(BCS0); in gdrst_mmio_write()
332 engine_mask |= BIT(VECS0); in gdrst_mmio_write()
336 engine_mask |= BIT(VCS1); in gdrst_mmio_write()
342 engine_mask &= vgpu->gvt->gt->info.engine_mask; in gdrst_mmio_write()
346 intel_gvt_reset_vgpu_locked(vgpu, false, engine_mask); in gdrst_mmio_write()
/linux-5.19.10/drivers/gpu/drm/i915/
Di915_gpu_error.h247 intel_engine_mask_t engine_mask, u32 dump_flags);
249 intel_engine_mask_t engine_mask, u32 dump_flags);
308 i915_capture_error_state(struct intel_gt *gt, intel_engine_mask_t engine_mask, u32 dump_flags) in i915_capture_error_state() argument
Di915_drv.h875 for ((tmp__) = (mask__) & (gt__)->info.engine_mask; \
1215 #define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id)) argument
1216 #define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id)
1221 ((gt)->info.engine_mask & \
Di915_gpu_error.c1611 intel_engine_mask_t engine_mask, in gt_record_engines() argument
1628 ee->hung = engine->mask & engine_mask; in gt_record_engines()
1986 __i915_gpu_coredump(struct intel_gt *gt, intel_engine_mask_t engine_mask, u32 dump_flags) in __i915_gpu_coredump() argument
2022 gt_record_engines(error->gt, engine_mask, compress, dump_flags); in __i915_gpu_coredump()
2036 i915_gpu_coredump(struct intel_gt *gt, intel_engine_mask_t engine_mask, u32 dump_flags) in i915_gpu_coredump() argument
2045 dump = __i915_gpu_coredump(gt, engine_mask, dump_flags); in i915_gpu_coredump()
2092 intel_engine_mask_t engine_mask, u32 dump_flags) in i915_capture_error_state() argument
2096 error = i915_gpu_coredump(gt, engine_mask, dump_flags); in i915_capture_error_state()
/linux-5.19.10/drivers/net/wireless/mediatek/mt76/
Dmt76x02_dfs.c617 u32 engine_mask; in mt76x02_dfs_tasklet() local
641 engine_mask = mt76_rr(dev, MT_BBP(DFS, 1)); in mt76x02_dfs_tasklet()
642 if (!(engine_mask & 0xf)) in mt76x02_dfs_tasklet()
648 if (!(engine_mask & (1 << i))) in mt76x02_dfs_tasklet()
/linux-5.19.10/drivers/gpu/drm/i915/selftests/
Dmock_gem_device.c213 to_gt(i915)->info.engine_mask = BIT(0); in mock_gem_device()
/linux-5.19.10/drivers/gpu/drm/i915/gt/uc/
Dintel_guc_submission.c3822 intel_engine_mask_t tmp, mask = b->engine_mask; in guc_irq_enable_breadcrumbs()
3835 intel_engine_mask_t tmp, mask = b->engine_mask; in guc_irq_disable_breadcrumbs()
3868 engine->breadcrumbs->engine_mask |= engine->mask; in guc_init_breadcrumbs()