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Searched refs:dyn_state (Results 1 – 25 of 29) sorted by relevance

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/linux-5.19.10/drivers/gpu/drm/amd/pm/legacy-dpm/
Dlegacy_dpm.c273 ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in amdgpu_parse_extended_power_table()
284 ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in amdgpu_parse_extended_power_table()
295 ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in amdgpu_parse_extended_power_table()
306 ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk, in amdgpu_parse_extended_power_table()
319 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk = in amdgpu_parse_extended_power_table()
322 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk = in amdgpu_parse_extended_power_table()
325 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc = in amdgpu_parse_extended_power_table()
327 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddci = in amdgpu_parse_extended_power_table()
338 adev->pm.dpm.dyn_state.phase_shedding_limits_table.entries = in amdgpu_parse_extended_power_table()
342 if (!adev->pm.dpm.dyn_state.phase_shedding_limits_table.entries) { in amdgpu_parse_extended_power_table()
[all …]
Dsi_dpm.c2251 struct amdgpu_ppm_table *ppm = adev->pm.dpm.dyn_state.ppm_table; in si_populate_smc_tdp_limits()
2632 &adev->pm.dpm.dyn_state.cac_leakage_table; in si_get_cac_std_voltage_max_min()
3036 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in si_get_vce_clock_voltage()
3234 return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_mclk_values, in btc_get_valid_mclk()
3241 return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_sclk_values, in btc_get_valid_sclk()
3294 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > adev->pm.dpm.dyn_state.mclk_sclk_ratio) in btc_adjust_clock_combinations()
3298 (adev->pm.dpm.dyn_state.mclk_sclk_ratio - 1)) / in btc_adjust_clock_combinations()
3299 adev->pm.dpm.dyn_state.mclk_sclk_ratio); in btc_adjust_clock_combinations()
3301 if ((pl->sclk - pl->mclk) > adev->pm.dpm.dyn_state.sclk_mclk_delta) in btc_adjust_clock_combinations()
3305 adev->pm.dpm.dyn_state.sclk_mclk_delta); in btc_adjust_clock_combinations()
[all …]
Dkv_dpm.c77 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_convert_vid2_to_vid7()
99 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_convert_vid7_to_vid2()
804 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_program_bootup_state()
906 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; in kv_populate_uvd_table()
979 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in kv_populate_vce_table()
1040 &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table; in kv_populate_samu_table()
1106 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; in kv_populate_acp_table()
1165 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_calculate_dfs_bypass_settings()
1511 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; in kv_update_uvd_dpm()
1547 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in kv_get_vce_boot_level()
[all …]
/linux-5.19.10/drivers/gpu/drm/radeon/
Dr600_dpm.c926 ret = r600_parse_clk_voltage_dep_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in r600_parse_extended_power_table()
935 ret = r600_parse_clk_voltage_dep_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in r600_parse_extended_power_table()
938 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries); in r600_parse_extended_power_table()
946 ret = r600_parse_clk_voltage_dep_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in r600_parse_extended_power_table()
949 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries); in r600_parse_extended_power_table()
950 kfree(rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries); in r600_parse_extended_power_table()
958 ret = r600_parse_clk_voltage_dep_table(&rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk, in r600_parse_extended_power_table()
961 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries); in r600_parse_extended_power_table()
962 kfree(rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries); in r600_parse_extended_power_table()
963 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries); in r600_parse_extended_power_table()
[all …]
Dbtc_dpm.c1229 return btc_find_valid_clock(&rdev->pm.dpm.dyn_state.valid_mclk_values, in btc_get_valid_mclk()
1236 return btc_find_valid_clock(&rdev->pm.dpm.dyn_state.valid_sclk_values, in btc_get_valid_sclk()
1279 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > rdev->pm.dpm.dyn_state.mclk_sclk_ratio) in btc_adjust_clock_combinations()
1283 (rdev->pm.dpm.dyn_state.mclk_sclk_ratio - 1)) / in btc_adjust_clock_combinations()
1284 rdev->pm.dpm.dyn_state.mclk_sclk_ratio); in btc_adjust_clock_combinations()
1286 if ((pl->sclk - pl->mclk) > rdev->pm.dpm.dyn_state.sclk_mclk_delta) in btc_adjust_clock_combinations()
1290 rdev->pm.dpm.dyn_state.sclk_mclk_delta); in btc_adjust_clock_combinations()
1317 if ((*vddc - *vddci) > rdev->pm.dpm.dyn_state.vddc_vddci_delta) { in btc_apply_voltage_delta_rules()
1319 (*vddc - rdev->pm.dpm.dyn_state.vddc_vddci_delta)); in btc_apply_voltage_delta_rules()
1323 if ((*vddci - *vddc) > rdev->pm.dpm.dyn_state.vddc_vddci_delta) { in btc_apply_voltage_delta_rules()
[all …]
Dci_dpm.c259 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries == NULL) in ci_populate_bapm_vddc_vid_sidd()
261 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count > 8) in ci_populate_bapm_vddc_vid_sidd()
263 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count != in ci_populate_bapm_vddc_vid_sidd()
264 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count) in ci_populate_bapm_vddc_vid_sidd()
267 for (i = 0; i < rdev->pm.dpm.dyn_state.cac_leakage_table.count; i++) { in ci_populate_bapm_vddc_vid_sidd()
269 lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1); in ci_populate_bapm_vddc_vid_sidd()
270 hi_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2); in ci_populate_bapm_vddc_vid_sidd()
271 hi2_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3); in ci_populate_bapm_vddc_vid_sidd()
273 lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc); in ci_populate_bapm_vddc_vid_sidd()
274 hi_vid[i] = ci_convert_to_vid((u16)rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage); in ci_populate_bapm_vddc_vid_sidd()
[all …]
Dsi_dpm.c2144 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table; in si_populate_smc_tdp_limits()
2517 &rdev->pm.dpm.dyn_state.cac_leakage_table; in si_get_cac_std_voltage_max_min()
2920 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in si_get_vce_clock_voltage()
3007 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in si_apply_state_adjust_rules()
3009 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; in si_apply_state_adjust_rules()
3029 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in si_apply_state_adjust_rules()
3031 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in si_apply_state_adjust_rules()
3033 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in si_apply_state_adjust_rules()
3135 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in si_apply_state_adjust_rules()
3138 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in si_apply_state_adjust_rules()
[all …]
Dni_dpm.c802 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in ni_apply_state_adjust_rules()
804 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; in ni_apply_state_adjust_rules()
873 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in ni_apply_state_adjust_rules()
876 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in ni_apply_state_adjust_rules()
879 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in ni_apply_state_adjust_rules()
882 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, in ni_apply_state_adjust_rules()
896 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) in ni_apply_state_adjust_rules()
899 if (ps->performance_levels[i].vddc < rdev->pm.dpm.dyn_state.min_vddc_for_pcie_gen2) in ni_apply_state_adjust_rules()
1012 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); in ni_patch_dependency_tables_based_on_leakage()
1015 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk); in ni_patch_dependency_tables_based_on_leakage()
[all …]
Dkv_dpm.c399 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_convert_vid2_to_vid7()
421 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_convert_vid7_to_vid2()
562 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_program_bootup_state()
664 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; in kv_populate_uvd_table()
737 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in kv_populate_vce_table()
798 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table; in kv_populate_samu_table()
864 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; in kv_populate_acp_table()
923 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_calculate_dfs_bypass_settings()
1248 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; in kv_update_uvd_dpm()
1284 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in kv_get_vce_boot_level()
[all …]
Drv770_dpm.c2261 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; in rv7xx_parse_pplib_clock_info()
2262 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; in rv7xx_parse_pplib_clock_info()
2263 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; in rv7xx_parse_pplib_clock_info()
2264 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci; in rv7xx_parse_pplib_clock_info()
Dradeon_kms.c536 *value = rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10; in radeon_info_ioctl()
/linux-5.19.10/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dprocesspptables.c1324 hwmgr->dyn_state.vddc_dependency_on_sclk = NULL; in init_clock_voltage_dependency()
1325 hwmgr->dyn_state.vddci_dependency_on_mclk = NULL; in init_clock_voltage_dependency()
1326 hwmgr->dyn_state.vddc_dependency_on_mclk = NULL; in init_clock_voltage_dependency()
1327 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL; in init_clock_voltage_dependency()
1328 hwmgr->dyn_state.mvdd_dependency_on_mclk = NULL; in init_clock_voltage_dependency()
1329 hwmgr->dyn_state.vce_clock_voltage_dependency_table = NULL; in init_clock_voltage_dependency()
1330 hwmgr->dyn_state.uvd_clock_voltage_dependency_table = NULL; in init_clock_voltage_dependency()
1331 hwmgr->dyn_state.samu_clock_voltage_dependency_table = NULL; in init_clock_voltage_dependency()
1332 hwmgr->dyn_state.acp_clock_voltage_dependency_table = NULL; in init_clock_voltage_dependency()
1333 hwmgr->dyn_state.ppm_parameter_table = NULL; in init_clock_voltage_dependency()
[all …]
Dsmu8_hwmgr.c73 hwmgr->dyn_state.vce_clock_voltage_dependency_table; in smu8_get_eclk_level()
104 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_get_sclk_level()
134 hwmgr->dyn_state.uvd_clock_voltage_dependency_table; in smu8_get_uvd_level()
262 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_construct_max_power_limits_table()
304 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt; in smu8_init_dynamic_state_adjustment_rule_settings()
405 &hwmgr->dyn_state.max_clock_voltage_on_ac); in smu8_get_system_info_data()
444 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_upload_pptable_to_smu()
446 hwmgr->dyn_state.vdd_gfx_dependency_on_sclk; in smu8_upload_pptable_to_smu()
448 hwmgr->dyn_state.acp_clock_voltage_dependency_table; in smu8_upload_pptable_to_smu()
450 hwmgr->dyn_state.uvd_clock_voltage_dependency_table; in smu8_upload_pptable_to_smu()
[all …]
Dsmu7_hwmgr.c338 hwmgr->dyn_state.mvdd_dependency_on_mclk); in smu7_construct_voltage_tables()
358 hwmgr->dyn_state.vddci_dependency_on_mclk); in smu7_construct_voltage_tables()
383 hwmgr->dyn_state.vddc_dependency_on_mclk); in smu7_construct_voltage_tables()
786 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu7_setup_dpm_tables_v0()
788 hwmgr->dyn_state.vddc_dependency_on_mclk; in smu7_setup_dpm_tables_v0()
790 hwmgr->dyn_state.cac_leakage_table; in smu7_setup_dpm_tables_v0()
840 allowed_vdd_mclk_table = hwmgr->dyn_state.vddci_dependency_on_mclk; in smu7_setup_dpm_tables_v0()
851 allowed_vdd_mclk_table = hwmgr->dyn_state.mvdd_dependency_on_mclk; in smu7_setup_dpm_tables_v0()
2143 hwmgr->dyn_state.max_clock_voltage_on_dc.vddc = in smu7_patch_clock_voltage_limits_with_vddc_leakage()
2433 hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = table_info->max_clock_voltage_on_ac.sclk; in smu7_set_private_data_based_on_pptable_v1()
[all …]
Dhwmgr.c245 if ((hwmgr->dyn_state.max_clock_voltage_on_dc.sclk == 0) || in hwmgr_hw_init()
246 (hwmgr->dyn_state.max_clock_voltage_on_dc.mclk == 0)) in hwmgr_hw_init()
247 hwmgr->dyn_state.max_clock_voltage_on_dc = in hwmgr_hw_init()
248 hwmgr->dyn_state.max_clock_voltage_on_ac; in hwmgr_hw_init()
Dprocess_pptables_v1_0.c582 hwmgr->dyn_state.cac_dtp_table = kzalloc(table_size, GFP_KERNEL); in get_cac_tdp_table()
584 if (NULL == hwmgr->dyn_state.cac_dtp_table) { in get_cac_tdp_table()
848 hwmgr->dyn_state.max_clock_voltage_on_dc.sclk = in init_clock_voltage_dependency()
850 hwmgr->dyn_state.max_clock_voltage_on_dc.mclk = in init_clock_voltage_dependency()
852 hwmgr->dyn_state.max_clock_voltage_on_dc.vddc = in init_clock_voltage_dependency()
854 hwmgr->dyn_state.max_clock_voltage_on_dc.vddci = in init_clock_voltage_dependency()
1219 kfree(hwmgr->dyn_state.cac_dtp_table); in pp_tables_v1_0_uninitialize()
1220 hwmgr->dyn_state.cac_dtp_table = NULL; in pp_tables_v1_0_uninitialize()
Dvega10_processpptables.c993 hwmgr->dyn_state.max_clock_voltage_on_dc.sclk = in init_powerplay_extended_tables()
995 hwmgr->dyn_state.max_clock_voltage_on_dc.mclk = in init_powerplay_extended_tables()
997 hwmgr->dyn_state.max_clock_voltage_on_dc.vddc = in init_powerplay_extended_tables()
999 hwmgr->dyn_state.max_clock_voltage_on_dc.vddci = in init_powerplay_extended_tables()
1232 kfree(hwmgr->dyn_state.cac_dtp_table); in vega10_pp_tables_uninitialize()
1233 hwmgr->dyn_state.cac_dtp_table = NULL; in vega10_pp_tables_uninitialize()
Dsmu10_hwmgr.c161 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt; in smu10_init_dynamic_state_adjustment_rule_settings()
177 &hwmgr->dyn_state.max_clock_voltage_on_ac); in smu10_get_system_info_data()
605 kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl); in smu10_hwmgr_backend_fini()
606 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL; in smu10_hwmgr_backend_fini()
Dppatomctrl.c1162 for (entry_id = 0; entry_id < hwmgr->dyn_state.vddc_dependency_on_sclk->count; entry_id++) { in atomctrl_get_voltage_evv()
1163 if (hwmgr->dyn_state.vddc_dependency_on_sclk->entries[entry_id].v == virtual_voltage_id) { in atomctrl_get_voltage_evv()
1169 if (entry_id >= hwmgr->dyn_state.vddc_dependency_on_sclk->count) { in atomctrl_get_voltage_evv()
1178 cpu_to_le32(hwmgr->dyn_state.vddc_dependency_on_sclk->entries[entry_id].clk); in atomctrl_get_voltage_evv()
Dvega10_hwmgr.c795 hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = in vega10_set_private_data_based_on_pptable()
797 hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = in vega10_set_private_data_based_on_pptable()
799 hwmgr->dyn_state.max_clock_voltage_on_ac.vddc = in vega10_set_private_data_based_on_pptable()
801 hwmgr->dyn_state.max_clock_voltage_on_ac.vddci = in vega10_set_private_data_based_on_pptable()
809 kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl); in vega10_hwmgr_backend_fini()
810 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL; in vega10_hwmgr_backend_fini()
3266 &(hwmgr->dyn_state.max_clock_voltage_on_ac) : in vega10_apply_state_adjust_rules()
3267 &(hwmgr->dyn_state.max_clock_voltage_on_dc); in vega10_apply_state_adjust_rules()
3296 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac); in vega10_apply_state_adjust_rules()
Dsmu_helper.c529 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt; in phm_initializa_dynamic_state_adjustment_rule_settings()
/linux-5.19.10/drivers/gpu/drm/amd/pm/powerplay/smumgr/
Dci_smumgr.c420 hwmgr->dyn_state.vddc_dependency_on_sclk, clock, in ci_populate_single_graphic_level()
432 hwmgr->dyn_state.vddc_phase_shed_limits_table, in ci_populate_single_graphic_level()
533 tdc_limit = (uint16_t)(hwmgr->dyn_state.cac_dtp_table->usTDC * 256); in ci_populate_tdc_limit()
586 PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.cac_leakage_table, in ci_populate_bapm_vddc_vid_sidd()
588 PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count <= 8, in ci_populate_bapm_vddc_vid_sidd()
590 …PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count == hwmgr->dyn_state.vddc_dependency_… in ci_populate_bapm_vddc_vid_sidd()
593 for (i = 0; (uint32_t) i < hwmgr->dyn_state.cac_leakage_table->count; i++) { in ci_populate_bapm_vddc_vid_sidd()
595 lo_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc1); in ci_populate_bapm_vddc_vid_sidd()
596 hi_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc2); in ci_populate_bapm_vddc_vid_sidd()
597 hi2_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc3); in ci_populate_bapm_vddc_vid_sidd()
[all …]
Diceland_smumgr.c325 tdc_limit = (uint16_t)(hwmgr->dyn_state.cac_dtp_table->usTDC * 256); in iceland_populate_tdc_limit()
376 struct phm_cac_tdp_table *cac_table = hwmgr->dyn_state.cac_dtp_table; in iceland_populate_bapm_vddc_base_leakage_sidd()
396 PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.cac_leakage_table, in iceland_populate_bapm_vddc_vid_sidd()
398 PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count <= 8, in iceland_populate_bapm_vddc_vid_sidd()
400 …PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count == hwmgr->dyn_state.vddc_dependency_… in iceland_populate_bapm_vddc_vid_sidd()
404 for (i = 0; (uint32_t) i < hwmgr->dyn_state.cac_leakage_table->count; i++) { in iceland_populate_bapm_vddc_vid_sidd()
405 lo_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc1); in iceland_populate_bapm_vddc_vid_sidd()
406 hi_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc2); in iceland_populate_bapm_vddc_vid_sidd()
540 PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.vddc_dependency_on_sclk, in iceland_get_std_voltage_value_sidd()
544 if (NULL == hwmgr->dyn_state.cac_leakage_table) { in iceland_get_std_voltage_value_sidd()
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/linux-5.19.10/drivers/gpu/drm/amd/pm/inc/
Damdgpu_dpm.h257 struct amdgpu_dpm_dynamic_state dyn_state; member
/linux-5.19.10/drivers/gpu/drm/amd/pm/powerplay/inc/
Dhwmgr.h779 struct phm_dynamic_state_info dyn_state; member

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