1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_HW_TYPES_H 27 #define DC_HW_TYPES_H 28 29 #include "os_types.h" 30 #include "fixed31_32.h" 31 #include "signal_types.h" 32 33 /****************************************************************************** 34 * Data types for Virtual HW Layer of DAL3. 35 * (see DAL3 design documents for HW Layer definition) 36 * 37 * The intended uses are: 38 * 1. Generation pseudocode sequences for HW programming. 39 * 2. Implementation of real HW programming by HW Sequencer of DAL3. 40 * 41 * Note: do *not* add any types which are *not* used for HW programming - this 42 * will ensure separation of Logic layer from HW layer. 43 ******************************************************************************/ 44 45 union large_integer { 46 struct { 47 uint32_t low_part; 48 int32_t high_part; 49 }; 50 51 struct { 52 uint32_t low_part; 53 int32_t high_part; 54 } u; 55 56 int64_t quad_part; 57 }; 58 59 #define PHYSICAL_ADDRESS_LOC union large_integer 60 61 enum dc_plane_addr_type { 62 PLN_ADDR_TYPE_GRAPHICS = 0, 63 PLN_ADDR_TYPE_GRPH_STEREO, 64 PLN_ADDR_TYPE_VIDEO_PROGRESSIVE, 65 PLN_ADDR_TYPE_RGBEA 66 }; 67 68 struct dc_plane_address { 69 enum dc_plane_addr_type type; 70 bool tmz_surface; 71 union { 72 struct{ 73 PHYSICAL_ADDRESS_LOC addr; 74 PHYSICAL_ADDRESS_LOC cursor_cache_addr; 75 PHYSICAL_ADDRESS_LOC meta_addr; 76 union large_integer dcc_const_color; 77 } grph; 78 79 /*stereo*/ 80 struct { 81 PHYSICAL_ADDRESS_LOC left_addr; 82 PHYSICAL_ADDRESS_LOC left_meta_addr; 83 union large_integer left_dcc_const_color; 84 85 PHYSICAL_ADDRESS_LOC right_addr; 86 PHYSICAL_ADDRESS_LOC right_meta_addr; 87 union large_integer right_dcc_const_color; 88 89 PHYSICAL_ADDRESS_LOC left_alpha_addr; 90 PHYSICAL_ADDRESS_LOC left_alpha_meta_addr; 91 union large_integer left_alpha_dcc_const_color; 92 93 PHYSICAL_ADDRESS_LOC right_alpha_addr; 94 PHYSICAL_ADDRESS_LOC right_alpha_meta_addr; 95 union large_integer right_alpha_dcc_const_color; 96 97 } grph_stereo; 98 99 /*video progressive*/ 100 struct { 101 PHYSICAL_ADDRESS_LOC luma_addr; 102 PHYSICAL_ADDRESS_LOC luma_meta_addr; 103 union large_integer luma_dcc_const_color; 104 105 PHYSICAL_ADDRESS_LOC chroma_addr; 106 PHYSICAL_ADDRESS_LOC chroma_meta_addr; 107 union large_integer chroma_dcc_const_color; 108 } video_progressive; 109 110 struct { 111 PHYSICAL_ADDRESS_LOC addr; 112 PHYSICAL_ADDRESS_LOC meta_addr; 113 union large_integer dcc_const_color; 114 115 PHYSICAL_ADDRESS_LOC alpha_addr; 116 PHYSICAL_ADDRESS_LOC alpha_meta_addr; 117 union large_integer alpha_dcc_const_color; 118 } rgbea; 119 }; 120 121 union large_integer page_table_base; 122 123 uint8_t vmid; 124 }; 125 126 struct dc_size { 127 int width; 128 int height; 129 }; 130 131 struct rect { 132 int x; 133 int y; 134 int width; 135 int height; 136 }; 137 138 struct plane_size { 139 /* Graphic surface pitch in pixels. 140 * In LINEAR_GENERAL mode, pitch 141 * is 32 pixel aligned. 142 */ 143 int surface_pitch; 144 int chroma_pitch; 145 struct rect surface_size; 146 struct rect chroma_size; 147 }; 148 149 struct dc_plane_dcc_param { 150 bool enable; 151 152 int meta_pitch; 153 bool independent_64b_blks; 154 uint8_t dcc_ind_blk; 155 156 int meta_pitch_c; 157 bool independent_64b_blks_c; 158 uint8_t dcc_ind_blk_c; 159 }; 160 161 /*Displayable pixel format in fb*/ 162 enum surface_pixel_format { 163 SURFACE_PIXEL_FORMAT_GRPH_BEGIN = 0, 164 /*TOBE REMOVED paletta 256 colors*/ 165 SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS = 166 SURFACE_PIXEL_FORMAT_GRPH_BEGIN, 167 /*16 bpp*/ 168 SURFACE_PIXEL_FORMAT_GRPH_ARGB1555, 169 /*16 bpp*/ 170 SURFACE_PIXEL_FORMAT_GRPH_RGB565, 171 /*32 bpp*/ 172 SURFACE_PIXEL_FORMAT_GRPH_ARGB8888, 173 /*32 bpp swaped*/ 174 SURFACE_PIXEL_FORMAT_GRPH_ABGR8888, 175 176 SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010, 177 /*swaped*/ 178 SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010, 179 /*TOBE REMOVED swaped, XR_BIAS has no differance 180 * for pixel layout than previous and we can 181 * delete this after discusion*/ 182 SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS, 183 /*64 bpp */ 184 SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616, 185 /*swapped*/ 186 SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616, 187 /*float*/ 188 SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F, 189 /*swaped & float*/ 190 SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F, 191 /*grow graphics here if necessary */ 192 SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX, 193 SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX, 194 SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT, 195 SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT, 196 SURFACE_PIXEL_FORMAT_GRPH_RGBE, 197 SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA, 198 SURFACE_PIXEL_FORMAT_VIDEO_BEGIN, 199 SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr = 200 SURFACE_PIXEL_FORMAT_VIDEO_BEGIN, 201 SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb, 202 SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr, 203 SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb, 204 SURFACE_PIXEL_FORMAT_SUBSAMPLE_END, 205 SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010 = 206 SURFACE_PIXEL_FORMAT_SUBSAMPLE_END, 207 SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102, 208 SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888, 209 SURFACE_PIXEL_FORMAT_INVALID 210 211 /*grow 444 video here if necessary */ 212 }; 213 214 215 216 /* Pixel format */ 217 enum pixel_format { 218 /*graph*/ 219 PIXEL_FORMAT_UNINITIALIZED, 220 PIXEL_FORMAT_INDEX8, 221 PIXEL_FORMAT_RGB565, 222 PIXEL_FORMAT_ARGB8888, 223 PIXEL_FORMAT_ARGB2101010, 224 PIXEL_FORMAT_ARGB2101010_XRBIAS, 225 PIXEL_FORMAT_FP16, 226 /*video*/ 227 PIXEL_FORMAT_420BPP8, 228 PIXEL_FORMAT_420BPP10, 229 /*end of pixel format definition*/ 230 PIXEL_FORMAT_INVALID, 231 232 PIXEL_FORMAT_GRPH_BEGIN = PIXEL_FORMAT_INDEX8, 233 PIXEL_FORMAT_GRPH_END = PIXEL_FORMAT_FP16, 234 PIXEL_FORMAT_VIDEO_BEGIN = PIXEL_FORMAT_420BPP8, 235 PIXEL_FORMAT_VIDEO_END = PIXEL_FORMAT_420BPP10, 236 PIXEL_FORMAT_UNKNOWN 237 }; 238 239 /* 240 * This structure holds a surface address. There could be multiple addresses 241 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such 242 * as frame durations and DCC format can also be set. 243 */ 244 #define DC_MAX_DIRTY_RECTS 3 245 struct dc_flip_addrs { 246 struct dc_plane_address address; 247 unsigned int flip_timestamp_in_us; 248 bool flip_immediate; 249 /* TODO: add flip duration for FreeSync */ 250 bool triplebuffer_flips; 251 unsigned int dirty_rect_count; 252 struct rect dirty_rects[DC_MAX_DIRTY_RECTS]; 253 }; 254 255 enum tile_split_values { 256 DC_DISPLAY_MICRO_TILING = 0x0, 257 DC_THIN_MICRO_TILING = 0x1, 258 DC_DEPTH_MICRO_TILING = 0x2, 259 DC_ROTATED_MICRO_TILING = 0x3, 260 }; 261 262 enum tripleBuffer_enable { 263 DC_TRIPLEBUFFER_DISABLE = 0x0, 264 DC_TRIPLEBUFFER_ENABLE = 0x1, 265 }; 266 267 /* TODO: These values come from hardware spec. We need to readdress this 268 * if they ever change. 269 */ 270 enum array_mode_values { 271 DC_ARRAY_LINEAR_GENERAL = 0, 272 DC_ARRAY_LINEAR_ALLIGNED, 273 DC_ARRAY_1D_TILED_THIN1, 274 DC_ARRAY_1D_TILED_THICK, 275 DC_ARRAY_2D_TILED_THIN1, 276 DC_ARRAY_PRT_TILED_THIN1, 277 DC_ARRAY_PRT_2D_TILED_THIN1, 278 DC_ARRAY_2D_TILED_THICK, 279 DC_ARRAY_2D_TILED_X_THICK, 280 DC_ARRAY_PRT_TILED_THICK, 281 DC_ARRAY_PRT_2D_TILED_THICK, 282 DC_ARRAY_PRT_3D_TILED_THIN1, 283 DC_ARRAY_3D_TILED_THIN1, 284 DC_ARRAY_3D_TILED_THICK, 285 DC_ARRAY_3D_TILED_X_THICK, 286 DC_ARRAY_PRT_3D_TILED_THICK, 287 }; 288 289 enum tile_mode_values { 290 DC_ADDR_SURF_MICRO_TILING_DISPLAY = 0x0, 291 DC_ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1, 292 }; 293 294 enum swizzle_mode_values { 295 DC_SW_LINEAR = 0, 296 DC_SW_256B_S = 1, 297 DC_SW_256_D = 2, 298 DC_SW_256_R = 3, 299 DC_SW_4KB_S = 5, 300 DC_SW_4KB_D = 6, 301 DC_SW_4KB_R = 7, 302 DC_SW_64KB_S = 9, 303 DC_SW_64KB_D = 10, 304 DC_SW_64KB_R = 11, 305 DC_SW_VAR_S = 13, 306 DC_SW_VAR_D = 14, 307 DC_SW_VAR_R = 15, 308 DC_SW_64KB_S_T = 17, 309 DC_SW_64KB_D_T = 18, 310 DC_SW_4KB_S_X = 21, 311 DC_SW_4KB_D_X = 22, 312 DC_SW_4KB_R_X = 23, 313 DC_SW_64KB_S_X = 25, 314 DC_SW_64KB_D_X = 26, 315 DC_SW_64KB_R_X = 27, 316 DC_SW_VAR_S_X = 29, 317 DC_SW_VAR_D_X = 30, 318 DC_SW_VAR_R_X = 31, 319 DC_SW_MAX = 32, 320 DC_SW_UNKNOWN = DC_SW_MAX 321 }; 322 323 union dc_tiling_info { 324 325 struct { 326 /* Specifies the number of memory banks for tiling 327 * purposes. 328 * Only applies to 2D and 3D tiling modes. 329 * POSSIBLE VALUES: 2,4,8,16 330 */ 331 unsigned int num_banks; 332 /* Specifies the number of tiles in the x direction 333 * to be incorporated into the same bank. 334 * Only applies to 2D and 3D tiling modes. 335 * POSSIBLE VALUES: 1,2,4,8 336 */ 337 unsigned int bank_width; 338 unsigned int bank_width_c; 339 /* Specifies the number of tiles in the y direction to 340 * be incorporated into the same bank. 341 * Only applies to 2D and 3D tiling modes. 342 * POSSIBLE VALUES: 1,2,4,8 343 */ 344 unsigned int bank_height; 345 unsigned int bank_height_c; 346 /* Specifies the macro tile aspect ratio. Only applies 347 * to 2D and 3D tiling modes. 348 */ 349 unsigned int tile_aspect; 350 unsigned int tile_aspect_c; 351 /* Specifies the number of bytes that will be stored 352 * contiguously for each tile. 353 * If the tile data requires more storage than this 354 * amount, it is split into multiple slices. 355 * This field must not be larger than 356 * GB_ADDR_CONFIG.DRAM_ROW_SIZE. 357 * Only applies to 2D and 3D tiling modes. 358 * For color render targets, TILE_SPLIT >= 256B. 359 */ 360 enum tile_split_values tile_split; 361 enum tile_split_values tile_split_c; 362 /* Specifies the addressing within a tile. 363 * 0x0 - DISPLAY_MICRO_TILING 364 * 0x1 - THIN_MICRO_TILING 365 * 0x2 - DEPTH_MICRO_TILING 366 * 0x3 - ROTATED_MICRO_TILING 367 */ 368 enum tile_mode_values tile_mode; 369 enum tile_mode_values tile_mode_c; 370 /* Specifies the number of pipes and how they are 371 * interleaved in the surface. 372 * Refer to memory addressing document for complete 373 * details and constraints. 374 */ 375 unsigned int pipe_config; 376 /* Specifies the tiling mode of the surface. 377 * THIN tiles use an 8x8x1 tile size. 378 * THICK tiles use an 8x8x4 tile size. 379 * 2D tiling modes rotate banks for successive Z slices 380 * 3D tiling modes rotate pipes and banks for Z slices 381 * Refer to memory addressing document for complete 382 * details and constraints. 383 */ 384 enum array_mode_values array_mode; 385 } gfx8; 386 387 struct { 388 enum swizzle_mode_values swizzle; 389 unsigned int num_pipes; 390 unsigned int max_compressed_frags; 391 unsigned int pipe_interleave; 392 393 unsigned int num_banks; 394 unsigned int num_shader_engines; 395 unsigned int num_rb_per_se; 396 bool shaderEnable; 397 398 bool meta_linear; 399 bool rb_aligned; 400 bool pipe_aligned; 401 unsigned int num_pkrs; 402 } gfx9; 403 }; 404 405 /* Rotation angle */ 406 enum dc_rotation_angle { 407 ROTATION_ANGLE_0 = 0, 408 ROTATION_ANGLE_90, 409 ROTATION_ANGLE_180, 410 ROTATION_ANGLE_270, 411 ROTATION_ANGLE_COUNT 412 }; 413 414 enum dc_scan_direction { 415 SCAN_DIRECTION_UNKNOWN = 0, 416 SCAN_DIRECTION_HORIZONTAL = 1, /* 0, 180 rotation */ 417 SCAN_DIRECTION_VERTICAL = 2, /* 90, 270 rotation */ 418 }; 419 420 struct dc_cursor_position { 421 uint32_t x; 422 uint32_t y; 423 424 uint32_t x_hotspot; 425 uint32_t y_hotspot; 426 427 /* 428 * This parameter indicates whether HW cursor should be enabled 429 */ 430 bool enable; 431 432 /* Translate cursor x/y by the source rectangle for each plane. */ 433 bool translate_by_source; 434 }; 435 436 struct dc_cursor_mi_param { 437 unsigned int pixel_clk_khz; 438 unsigned int ref_clk_khz; 439 struct rect viewport; 440 struct fixed31_32 h_scale_ratio; 441 struct fixed31_32 v_scale_ratio; 442 enum dc_rotation_angle rotation; 443 bool mirror; 444 }; 445 446 /* IPP related types */ 447 448 enum { 449 GAMMA_RGB_256_ENTRIES = 256, 450 GAMMA_RGB_FLOAT_1024_ENTRIES = 1024, 451 GAMMA_CS_TFM_1D_ENTRIES = 4096, 452 GAMMA_CUSTOM_ENTRIES = 4096, 453 GAMMA_MAX_ENTRIES = 4096 454 }; 455 456 enum dc_gamma_type { 457 GAMMA_RGB_256 = 1, 458 GAMMA_RGB_FLOAT_1024 = 2, 459 GAMMA_CS_TFM_1D = 3, 460 GAMMA_CUSTOM = 4, 461 }; 462 463 struct dc_csc_transform { 464 uint16_t matrix[12]; 465 bool enable_adjustment; 466 }; 467 468 struct dc_rgb_fixed { 469 struct fixed31_32 red; 470 struct fixed31_32 green; 471 struct fixed31_32 blue; 472 }; 473 474 struct dc_gamma { 475 struct kref refcount; 476 enum dc_gamma_type type; 477 unsigned int num_entries; 478 479 struct dc_gamma_entries { 480 struct fixed31_32 red[GAMMA_MAX_ENTRIES]; 481 struct fixed31_32 green[GAMMA_MAX_ENTRIES]; 482 struct fixed31_32 blue[GAMMA_MAX_ENTRIES]; 483 } entries; 484 485 /* private to DC core */ 486 struct dc_context *ctx; 487 488 /* is_identity is used for RGB256 gamma identity which can also be programmed in INPUT_LUT. 489 * is_logical_identity indicates the given gamma ramp regardless of type is identity. 490 */ 491 bool is_identity; 492 }; 493 494 /* Used by both ipp amd opp functions*/ 495 /* TODO: to be consolidated with enum color_space */ 496 497 /* 498 * This enum is for programming CURSOR_MODE register field. What this register 499 * should be programmed to depends on OS requested cursor shape flags and what 500 * we stored in the cursor surface. 501 */ 502 enum dc_cursor_color_format { 503 CURSOR_MODE_MONO, 504 CURSOR_MODE_COLOR_1BIT_AND, 505 CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA, 506 CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA, 507 CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED, 508 CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED 509 }; 510 511 /* 512 * This is all the parameters required by DAL in order to update the cursor 513 * attributes, including the new cursor image surface address, size, hotspot 514 * location, color format, etc. 515 */ 516 517 union dc_cursor_attribute_flags { 518 struct { 519 uint32_t ENABLE_MAGNIFICATION:1; 520 uint32_t INVERSE_TRANSPARENT_CLAMPING:1; 521 uint32_t HORIZONTAL_MIRROR:1; 522 uint32_t VERTICAL_MIRROR:1; 523 uint32_t INVERT_PIXEL_DATA:1; 524 uint32_t ZERO_EXPANSION:1; 525 uint32_t MIN_MAX_INVERT:1; 526 uint32_t ENABLE_CURSOR_DEGAMMA:1; 527 uint32_t RESERVED:24; 528 } bits; 529 uint32_t value; 530 }; 531 532 struct dc_cursor_attributes { 533 PHYSICAL_ADDRESS_LOC address; 534 uint32_t pitch; 535 536 /* Width and height should correspond to cursor surface width x heigh */ 537 uint32_t width; 538 uint32_t height; 539 540 enum dc_cursor_color_format color_format; 541 uint32_t sdr_white_level; // for boosting (SDR) cursor in HDR mode 542 543 /* In case we support HW Cursor rotation in the future */ 544 enum dc_rotation_angle rotation_angle; 545 546 union dc_cursor_attribute_flags attribute_flags; 547 }; 548 549 struct dpp_cursor_attributes { 550 int bias; 551 int scale; 552 }; 553 554 /* OPP */ 555 556 enum dc_color_space { 557 COLOR_SPACE_UNKNOWN, 558 COLOR_SPACE_SRGB, 559 COLOR_SPACE_XR_RGB, 560 COLOR_SPACE_SRGB_LIMITED, 561 COLOR_SPACE_MSREF_SCRGB, 562 COLOR_SPACE_YCBCR601, 563 COLOR_SPACE_YCBCR709, 564 COLOR_SPACE_XV_YCC_709, 565 COLOR_SPACE_XV_YCC_601, 566 COLOR_SPACE_YCBCR601_LIMITED, 567 COLOR_SPACE_YCBCR709_LIMITED, 568 COLOR_SPACE_2020_RGB_FULLRANGE, 569 COLOR_SPACE_2020_RGB_LIMITEDRANGE, 570 COLOR_SPACE_2020_YCBCR, 571 COLOR_SPACE_ADOBERGB, 572 COLOR_SPACE_DCIP3, 573 COLOR_SPACE_DISPLAYNATIVE, 574 COLOR_SPACE_DOLBYVISION, 575 COLOR_SPACE_APPCTRL, 576 COLOR_SPACE_CUSTOMPOINTS, 577 COLOR_SPACE_YCBCR709_BLACK, 578 }; 579 580 enum dc_dither_option { 581 DITHER_OPTION_DEFAULT, 582 DITHER_OPTION_DISABLE, 583 DITHER_OPTION_FM6, 584 DITHER_OPTION_FM8, 585 DITHER_OPTION_FM10, 586 DITHER_OPTION_SPATIAL6_FRAME_RANDOM, 587 DITHER_OPTION_SPATIAL8_FRAME_RANDOM, 588 DITHER_OPTION_SPATIAL10_FRAME_RANDOM, 589 DITHER_OPTION_SPATIAL6, 590 DITHER_OPTION_SPATIAL8, 591 DITHER_OPTION_SPATIAL10, 592 DITHER_OPTION_TRUN6, 593 DITHER_OPTION_TRUN8, 594 DITHER_OPTION_TRUN10, 595 DITHER_OPTION_TRUN10_SPATIAL8, 596 DITHER_OPTION_TRUN10_SPATIAL6, 597 DITHER_OPTION_TRUN10_FM8, 598 DITHER_OPTION_TRUN10_FM6, 599 DITHER_OPTION_TRUN10_SPATIAL8_FM6, 600 DITHER_OPTION_SPATIAL10_FM8, 601 DITHER_OPTION_SPATIAL10_FM6, 602 DITHER_OPTION_TRUN8_SPATIAL6, 603 DITHER_OPTION_TRUN8_FM6, 604 DITHER_OPTION_SPATIAL8_FM6, 605 DITHER_OPTION_MAX = DITHER_OPTION_SPATIAL8_FM6, 606 DITHER_OPTION_INVALID 607 }; 608 609 enum dc_quantization_range { 610 QUANTIZATION_RANGE_UNKNOWN, 611 QUANTIZATION_RANGE_FULL, 612 QUANTIZATION_RANGE_LIMITED 613 }; 614 615 enum dc_dynamic_expansion { 616 DYN_EXPANSION_AUTO, 617 DYN_EXPANSION_DISABLE 618 }; 619 620 /* XFM */ 621 622 /* used in struct dc_plane_state */ 623 struct scaling_taps { 624 uint32_t v_taps; 625 uint32_t h_taps; 626 uint32_t v_taps_c; 627 uint32_t h_taps_c; 628 bool integer_scaling; 629 }; 630 631 enum dc_timing_standard { 632 DC_TIMING_STANDARD_UNDEFINED, 633 DC_TIMING_STANDARD_DMT, 634 DC_TIMING_STANDARD_GTF, 635 DC_TIMING_STANDARD_CVT, 636 DC_TIMING_STANDARD_CVT_RB, 637 DC_TIMING_STANDARD_CEA770, 638 DC_TIMING_STANDARD_CEA861, 639 DC_TIMING_STANDARD_HDMI, 640 DC_TIMING_STANDARD_TV_NTSC, 641 DC_TIMING_STANDARD_TV_NTSC_J, 642 DC_TIMING_STANDARD_TV_PAL, 643 DC_TIMING_STANDARD_TV_PAL_M, 644 DC_TIMING_STANDARD_TV_PAL_CN, 645 DC_TIMING_STANDARD_TV_SECAM, 646 DC_TIMING_STANDARD_EXPLICIT, 647 /*!< For explicit timings from EDID, VBIOS, etc.*/ 648 DC_TIMING_STANDARD_USER_OVERRIDE, 649 /*!< For mode timing override by user*/ 650 DC_TIMING_STANDARD_MAX 651 }; 652 653 enum dc_color_depth { 654 COLOR_DEPTH_UNDEFINED, 655 COLOR_DEPTH_666, 656 COLOR_DEPTH_888, 657 COLOR_DEPTH_101010, 658 COLOR_DEPTH_121212, 659 COLOR_DEPTH_141414, 660 COLOR_DEPTH_161616, 661 COLOR_DEPTH_999, 662 COLOR_DEPTH_111111, 663 COLOR_DEPTH_COUNT 664 }; 665 666 enum dc_pixel_encoding { 667 PIXEL_ENCODING_UNDEFINED, 668 PIXEL_ENCODING_RGB, 669 PIXEL_ENCODING_YCBCR422, 670 PIXEL_ENCODING_YCBCR444, 671 PIXEL_ENCODING_YCBCR420, 672 PIXEL_ENCODING_COUNT 673 }; 674 675 enum dc_aspect_ratio { 676 ASPECT_RATIO_NO_DATA, 677 ASPECT_RATIO_4_3, 678 ASPECT_RATIO_16_9, 679 ASPECT_RATIO_64_27, 680 ASPECT_RATIO_256_135, 681 ASPECT_RATIO_FUTURE 682 }; 683 684 enum scanning_type { 685 SCANNING_TYPE_NODATA = 0, 686 SCANNING_TYPE_OVERSCAN, 687 SCANNING_TYPE_UNDERSCAN, 688 SCANNING_TYPE_FUTURE, 689 SCANNING_TYPE_UNDEFINED 690 }; 691 692 struct dc_crtc_timing_flags { 693 uint32_t INTERLACE :1; 694 uint32_t HSYNC_POSITIVE_POLARITY :1; /* when set to 1, 695 it is positive polarity --reversed with dal1 or video bios define*/ 696 uint32_t VSYNC_POSITIVE_POLARITY :1; /* when set to 1, 697 it is positive polarity --reversed with dal1 or video bios define*/ 698 699 uint32_t HORZ_COUNT_BY_TWO:1; 700 701 uint32_t EXCLUSIVE_3D :1; /* if this bit set, 702 timing can be driven in 3D format only 703 and there is no corresponding 2D timing*/ 704 uint32_t RIGHT_EYE_3D_POLARITY :1; /* 1 - means right eye polarity 705 (right eye = '1', left eye = '0') */ 706 uint32_t SUB_SAMPLE_3D :1; /* 1 - means left/right images subsampled 707 when mixed into 3D image. 0 - means summation (3D timing is doubled)*/ 708 uint32_t USE_IN_3D_VIEW_ONLY :1; /* Do not use this timing in 2D View, 709 because corresponding 2D timing also present in the list*/ 710 uint32_t STEREO_3D_PREFERENCE :1; /* Means this is 2D timing 711 and we want to match priority of corresponding 3D timing*/ 712 uint32_t Y_ONLY :1; 713 714 uint32_t YCBCR420 :1; /* TODO: shouldn't need this flag, should be a separate pixel format */ 715 uint32_t DTD_COUNTER :5; /* values 1 to 16 */ 716 717 uint32_t FORCE_HDR :1; 718 719 /* HDMI 2.0 - Support scrambling for TMDS character 720 * rates less than or equal to 340Mcsc */ 721 uint32_t LTE_340MCSC_SCRAMBLE:1; 722 723 uint32_t DSC : 1; /* Use DSC with this timing */ 724 #ifndef TRIM_FSFT 725 uint32_t FAST_TRANSPORT: 1; 726 #endif 727 uint32_t VBLANK_SYNCHRONIZABLE: 1; 728 }; 729 730 enum dc_timing_3d_format { 731 TIMING_3D_FORMAT_NONE, 732 TIMING_3D_FORMAT_FRAME_ALTERNATE, /* No stereosync at all*/ 733 TIMING_3D_FORMAT_INBAND_FA, /* Inband Frame Alternate (DVI/DP)*/ 734 TIMING_3D_FORMAT_DP_HDMI_INBAND_FA, /* Inband FA to HDMI Frame Pack*/ 735 /* for active DP-HDMI dongle*/ 736 TIMING_3D_FORMAT_SIDEBAND_FA, /* Sideband Frame Alternate (eDP)*/ 737 TIMING_3D_FORMAT_HW_FRAME_PACKING, 738 TIMING_3D_FORMAT_SW_FRAME_PACKING, 739 TIMING_3D_FORMAT_ROW_INTERLEAVE, 740 TIMING_3D_FORMAT_COLUMN_INTERLEAVE, 741 TIMING_3D_FORMAT_PIXEL_INTERLEAVE, 742 TIMING_3D_FORMAT_SIDE_BY_SIDE, 743 TIMING_3D_FORMAT_TOP_AND_BOTTOM, 744 TIMING_3D_FORMAT_SBS_SW_PACKED, 745 /* Side-by-side, packed by application/driver into 2D frame*/ 746 TIMING_3D_FORMAT_TB_SW_PACKED, 747 /* Top-and-bottom, packed by application/driver into 2D frame*/ 748 749 TIMING_3D_FORMAT_MAX, 750 }; 751 752 struct dc_dsc_config { 753 uint32_t num_slices_h; /* Number of DSC slices - horizontal */ 754 uint32_t num_slices_v; /* Number of DSC slices - vertical */ 755 uint32_t bits_per_pixel; /* DSC target bitrate in 1/16 of bpp (e.g. 128 -> 8bpp) */ 756 bool block_pred_enable; /* DSC block prediction enable */ 757 uint32_t linebuf_depth; /* DSC line buffer depth */ 758 uint32_t version_minor; /* DSC minor version. Full version is formed as 1.version_minor. */ 759 bool ycbcr422_simple; /* Tell DSC engine to convert YCbCr 4:2:2 to 'YCbCr 4:2:2 simple'. */ 760 int32_t rc_buffer_size; /* DSC RC buffer block size in bytes */ 761 #if defined(CONFIG_DRM_AMD_DC_DCN) 762 bool is_frl; /* indicate if DSC is applied based on HDMI FRL sink's capability */ 763 #endif 764 bool is_dp; /* indicate if DSC is applied based on DP's capability */ 765 uint32_t mst_pbn; /* pbn of display on dsc mst hub */ 766 }; 767 struct dc_crtc_timing { 768 uint32_t h_total; 769 uint32_t h_border_left; 770 uint32_t h_addressable; 771 uint32_t h_border_right; 772 uint32_t h_front_porch; 773 uint32_t h_sync_width; 774 775 uint32_t v_total; 776 uint32_t v_border_top; 777 uint32_t v_addressable; 778 uint32_t v_border_bottom; 779 uint32_t v_front_porch; 780 uint32_t v_sync_width; 781 782 uint32_t pix_clk_100hz; 783 784 uint32_t vic; 785 uint32_t hdmi_vic; 786 enum dc_timing_3d_format timing_3d_format; 787 enum dc_color_depth display_color_depth; 788 enum dc_pixel_encoding pixel_encoding; 789 enum dc_aspect_ratio aspect_ratio; 790 enum scanning_type scan_type; 791 792 #ifndef TRIM_FSFT 793 uint32_t fast_transport_output_rate_100hz; 794 #endif 795 796 struct dc_crtc_timing_flags flags; 797 uint32_t dsc_fixed_bits_per_pixel_x16; /* DSC target bitrate in 1/16 of bpp (e.g. 128 -> 8bpp) */ 798 struct dc_dsc_config dsc_cfg; 799 }; 800 801 enum trigger_delay { 802 TRIGGER_DELAY_NEXT_PIXEL = 0, 803 TRIGGER_DELAY_NEXT_LINE, 804 }; 805 806 enum crtc_event { 807 CRTC_EVENT_VSYNC_RISING = 0, 808 CRTC_EVENT_VSYNC_FALLING 809 }; 810 811 struct crtc_trigger_info { 812 bool enabled; 813 struct dc_stream_state *event_source; 814 enum crtc_event event; 815 enum trigger_delay delay; 816 }; 817 818 struct dc_crtc_timing_adjust { 819 uint32_t v_total_min; 820 uint32_t v_total_max; 821 uint32_t v_total_mid; 822 uint32_t v_total_mid_frame_num; 823 }; 824 825 826 /* Passed on init */ 827 enum vram_type { 828 VIDEO_MEMORY_TYPE_GDDR5 = 2, 829 VIDEO_MEMORY_TYPE_DDR3 = 3, 830 VIDEO_MEMORY_TYPE_DDR4 = 4, 831 VIDEO_MEMORY_TYPE_HBM = 5, 832 VIDEO_MEMORY_TYPE_GDDR6 = 6, 833 }; 834 835 enum dwb_cnv_out_bpc { 836 DWB_CNV_OUT_BPC_8BPC = 0, 837 DWB_CNV_OUT_BPC_10BPC = 1, 838 }; 839 840 enum dwb_output_depth { 841 DWB_OUTPUT_PIXEL_DEPTH_8BPC = 0, 842 DWB_OUTPUT_PIXEL_DEPTH_10BPC = 1, 843 }; 844 845 enum dwb_capture_rate { 846 dwb_capture_rate_0 = 0, /* Every frame is captured. */ 847 dwb_capture_rate_1 = 1, /* Every other frame is captured. */ 848 dwb_capture_rate_2 = 2, /* Every 3rd frame is captured. */ 849 dwb_capture_rate_3 = 3, /* Every 4th frame is captured. */ 850 }; 851 852 enum dwb_scaler_mode { 853 dwb_scaler_mode_bypass444 = 0, 854 dwb_scaler_mode_rgb444 = 1, 855 dwb_scaler_mode_yuv444 = 2, 856 dwb_scaler_mode_yuv420 = 3 857 }; 858 859 enum dwb_subsample_position { 860 DWB_INTERSTITIAL_SUBSAMPLING = 0, 861 DWB_COSITED_SUBSAMPLING = 1 862 }; 863 864 enum dwb_stereo_eye_select { 865 DWB_STEREO_EYE_LEFT = 1, /* Capture left eye only */ 866 DWB_STEREO_EYE_RIGHT = 2, /* Capture right eye only */ 867 }; 868 869 enum dwb_stereo_type { 870 DWB_STEREO_TYPE_FRAME_PACKING = 0, /* Frame packing */ 871 DWB_STEREO_TYPE_FRAME_SEQUENTIAL = 3, /* Frame sequential */ 872 }; 873 874 enum dwb_out_format { 875 DWB_OUT_FORMAT_32BPP_ARGB = 0, 876 DWB_OUT_FORMAT_32BPP_RGBA = 1, 877 DWB_OUT_FORMAT_64BPP_ARGB = 2, 878 DWB_OUT_FORMAT_64BPP_RGBA = 3 879 }; 880 881 enum dwb_out_denorm { 882 DWB_OUT_DENORM_10BPC = 0, 883 DWB_OUT_DENORM_8BPC = 1, 884 DWB_OUT_DENORM_BYPASS = 2 885 }; 886 887 enum cm_gamut_remap_select { 888 CM_GAMUT_REMAP_MODE_BYPASS = 0, 889 CM_GAMUT_REMAP_MODE_RAMA_COEFF, 890 CM_GAMUT_REMAP_MODE_RAMB_COEFF, 891 CM_GAMUT_REMAP_MODE_RESERVED 892 }; 893 894 enum cm_gamut_coef_format { 895 CM_GAMUT_REMAP_COEF_FORMAT_S2_13 = 0, 896 CM_GAMUT_REMAP_COEF_FORMAT_S3_12 = 1 897 }; 898 899 struct mcif_warmup_params { 900 union large_integer start_address; 901 unsigned int address_increment; 902 unsigned int region_size; 903 unsigned int p_vmid; 904 }; 905 906 #define MCIF_BUF_COUNT 4 907 908 struct mcif_buf_params { 909 unsigned long long luma_address[MCIF_BUF_COUNT]; 910 unsigned long long chroma_address[MCIF_BUF_COUNT]; 911 unsigned int luma_pitch; 912 unsigned int chroma_pitch; 913 unsigned int warmup_pitch; 914 unsigned int swlock; 915 unsigned int p_vmid; 916 }; 917 918 919 #define MAX_TG_COLOR_VALUE 0x3FF 920 struct tg_color { 921 /* Maximum 10 bits color value */ 922 uint16_t color_r_cr; 923 uint16_t color_g_y; 924 uint16_t color_b_cb; 925 }; 926 927 #endif /* DC_HW_TYPES_H */ 928 929