1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 #include "logger_types.h" 32 #if defined(CONFIG_DRM_AMD_DC_HDCP) 33 #include "hdcp_types.h" 34 #endif 35 #include "gpio_types.h" 36 #include "link_service_types.h" 37 #include "grph_object_ctrl_defs.h" 38 #include <inc/hw/opp.h> 39 40 #include "inc/hw_sequencer.h" 41 #include "inc/compressor.h" 42 #include "inc/hw/dmcu.h" 43 #include "dml/display_mode_lib.h" 44 45 /* forward declaration */ 46 struct aux_payload; 47 struct set_config_cmd_payload; 48 struct dmub_notification; 49 50 #define DC_VER "3.2.187" 51 52 #define MAX_SURFACES 3 53 #define MAX_PLANES 6 54 #define MAX_STREAMS 6 55 #define MAX_SINKS_PER_LINK 4 56 #define MIN_VIEWPORT_SIZE 12 57 #define MAX_NUM_EDP 2 58 59 /******************************************************************************* 60 * Display Core Interfaces 61 ******************************************************************************/ 62 struct dc_versions { 63 const char *dc_ver; 64 struct dmcu_version dmcu_version; 65 }; 66 67 enum dp_protocol_version { 68 DP_VERSION_1_4, 69 }; 70 71 enum dc_plane_type { 72 DC_PLANE_TYPE_INVALID, 73 DC_PLANE_TYPE_DCE_RGB, 74 DC_PLANE_TYPE_DCE_UNDERLAY, 75 DC_PLANE_TYPE_DCN_UNIVERSAL, 76 }; 77 78 // Sizes defined as multiples of 64KB 79 enum det_size { 80 DET_SIZE_DEFAULT = 0, 81 DET_SIZE_192KB = 3, 82 DET_SIZE_256KB = 4, 83 DET_SIZE_320KB = 5, 84 DET_SIZE_384KB = 6 85 }; 86 87 88 struct dc_plane_cap { 89 enum dc_plane_type type; 90 uint32_t blends_with_above : 1; 91 uint32_t blends_with_below : 1; 92 uint32_t per_pixel_alpha : 1; 93 struct { 94 uint32_t argb8888 : 1; 95 uint32_t nv12 : 1; 96 uint32_t fp16 : 1; 97 uint32_t p010 : 1; 98 uint32_t ayuv : 1; 99 } pixel_format_support; 100 // max upscaling factor x1000 101 // upscaling factors are always >= 1 102 // for example, 1080p -> 8K is 4.0, or 4000 raw value 103 struct { 104 uint32_t argb8888; 105 uint32_t nv12; 106 uint32_t fp16; 107 } max_upscale_factor; 108 // max downscale factor x1000 109 // downscale factors are always <= 1 110 // for example, 8K -> 1080p is 0.25, or 250 raw value 111 struct { 112 uint32_t argb8888; 113 uint32_t nv12; 114 uint32_t fp16; 115 } max_downscale_factor; 116 // minimal width/height 117 uint32_t min_width; 118 uint32_t min_height; 119 }; 120 121 // Color management caps (DPP and MPC) 122 struct rom_curve_caps { 123 uint16_t srgb : 1; 124 uint16_t bt2020 : 1; 125 uint16_t gamma2_2 : 1; 126 uint16_t pq : 1; 127 uint16_t hlg : 1; 128 }; 129 130 struct dpp_color_caps { 131 uint16_t dcn_arch : 1; // all DCE generations treated the same 132 // input lut is different than most LUTs, just plain 256-entry lookup 133 uint16_t input_lut_shared : 1; // shared with DGAM 134 uint16_t icsc : 1; 135 uint16_t dgam_ram : 1; 136 uint16_t post_csc : 1; // before gamut remap 137 uint16_t gamma_corr : 1; 138 139 // hdr_mult and gamut remap always available in DPP (in that order) 140 // 3d lut implies shaper LUT, 141 // it may be shared with MPC - check MPC:shared_3d_lut flag 142 uint16_t hw_3d_lut : 1; 143 uint16_t ogam_ram : 1; // blnd gam 144 uint16_t ocsc : 1; 145 uint16_t dgam_rom_for_yuv : 1; 146 struct rom_curve_caps dgam_rom_caps; 147 struct rom_curve_caps ogam_rom_caps; 148 }; 149 150 struct mpc_color_caps { 151 uint16_t gamut_remap : 1; 152 uint16_t ogam_ram : 1; 153 uint16_t ocsc : 1; 154 uint16_t num_3dluts : 3; //3d lut always assumes a preceding shaper LUT 155 uint16_t shared_3d_lut:1; //can be in either DPP or MPC, but single instance 156 157 struct rom_curve_caps ogam_rom_caps; 158 }; 159 160 struct dc_color_caps { 161 struct dpp_color_caps dpp; 162 struct mpc_color_caps mpc; 163 }; 164 165 struct dc_caps { 166 uint32_t max_streams; 167 uint32_t max_links; 168 uint32_t max_audios; 169 uint32_t max_slave_planes; 170 uint32_t max_slave_yuv_planes; 171 uint32_t max_slave_rgb_planes; 172 uint32_t max_planes; 173 uint32_t max_downscale_ratio; 174 uint32_t i2c_speed_in_khz; 175 uint32_t i2c_speed_in_khz_hdcp; 176 uint32_t dmdata_alloc_size; 177 unsigned int max_cursor_size; 178 unsigned int max_video_width; 179 unsigned int min_horizontal_blanking_period; 180 int linear_pitch_alignment; 181 bool dcc_const_color; 182 bool dynamic_audio; 183 bool is_apu; 184 bool dual_link_dvi; 185 bool post_blend_color_processing; 186 bool force_dp_tps4_for_cp2520; 187 bool disable_dp_clk_share; 188 bool psp_setup_panel_mode; 189 bool extended_aux_timeout_support; 190 bool dmcub_support; 191 bool zstate_support; 192 uint32_t num_of_internal_disp; 193 enum dp_protocol_version max_dp_protocol_version; 194 unsigned int mall_size_per_mem_channel; 195 unsigned int mall_size_total; 196 unsigned int cursor_cache_size; 197 struct dc_plane_cap planes[MAX_PLANES]; 198 struct dc_color_caps color; 199 bool dp_hpo; 200 bool hdmi_frl_pcon_support; 201 bool edp_dsc_support; 202 bool vbios_lttpr_aware; 203 bool vbios_lttpr_enable; 204 uint32_t max_otg_num; 205 }; 206 207 struct dc_bug_wa { 208 bool no_connect_phy_config; 209 bool dedcn20_305_wa; 210 bool skip_clock_update; 211 bool lt_early_cr_pattern; 212 }; 213 214 struct dc_dcc_surface_param { 215 struct dc_size surface_size; 216 enum surface_pixel_format format; 217 enum swizzle_mode_values swizzle_mode; 218 enum dc_scan_direction scan; 219 }; 220 221 struct dc_dcc_setting { 222 unsigned int max_compressed_blk_size; 223 unsigned int max_uncompressed_blk_size; 224 bool independent_64b_blks; 225 //These bitfields to be used starting with DCN 226 struct { 227 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN (the worst compression case) 228 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 229 uint32_t dcc_256_128_128 : 1; //available starting with DCN 230 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN (the best compression case) 231 } dcc_controls; 232 }; 233 234 struct dc_surface_dcc_cap { 235 union { 236 struct { 237 struct dc_dcc_setting rgb; 238 } grph; 239 240 struct { 241 struct dc_dcc_setting luma; 242 struct dc_dcc_setting chroma; 243 } video; 244 }; 245 246 bool capable; 247 bool const_color_support; 248 }; 249 250 struct dc_static_screen_params { 251 struct { 252 bool force_trigger; 253 bool cursor_update; 254 bool surface_update; 255 bool overlay_update; 256 } triggers; 257 unsigned int num_frames; 258 }; 259 260 261 /* Surface update type is used by dc_update_surfaces_and_stream 262 * The update type is determined at the very beginning of the function based 263 * on parameters passed in and decides how much programming (or updating) is 264 * going to be done during the call. 265 * 266 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 267 * logical calculations or hardware register programming. This update MUST be 268 * ISR safe on windows. Currently fast update will only be used to flip surface 269 * address. 270 * 271 * UPDATE_TYPE_MED is used for slower updates which require significant hw 272 * re-programming however do not affect bandwidth consumption or clock 273 * requirements. At present, this is the level at which front end updates 274 * that do not require us to run bw_calcs happen. These are in/out transfer func 275 * updates, viewport offset changes, recout size changes and pixel depth changes. 276 * This update can be done at ISR, but we want to minimize how often this happens. 277 * 278 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 279 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 280 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 281 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 282 * a full update. This cannot be done at ISR level and should be a rare event. 283 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 284 * underscan we don't expect to see this call at all. 285 */ 286 287 enum surface_update_type { 288 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 289 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 290 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 291 }; 292 293 /* Forward declaration*/ 294 struct dc; 295 struct dc_plane_state; 296 struct dc_state; 297 298 299 struct dc_cap_funcs { 300 bool (*get_dcc_compression_cap)(const struct dc *dc, 301 const struct dc_dcc_surface_param *input, 302 struct dc_surface_dcc_cap *output); 303 }; 304 305 struct link_training_settings; 306 307 union allow_lttpr_non_transparent_mode { 308 struct { 309 bool DP1_4A : 1; 310 bool DP2_0 : 1; 311 } bits; 312 unsigned char raw; 313 }; 314 315 /* Structure to hold configuration flags set by dm at dc creation. */ 316 struct dc_config { 317 bool gpu_vm_support; 318 bool disable_disp_pll_sharing; 319 bool fbc_support; 320 bool disable_fractional_pwm; 321 bool allow_seamless_boot_optimization; 322 bool seamless_boot_edp_requested; 323 bool edp_not_connected; 324 bool edp_no_power_sequencing; 325 bool force_enum_edp; 326 bool forced_clocks; 327 union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode; 328 bool multi_mon_pp_mclk_switch; 329 bool disable_dmcu; 330 bool enable_4to1MPC; 331 bool enable_windowed_mpo_odm; 332 uint32_t allow_edp_hotplug_detection; 333 bool clamp_min_dcfclk; 334 uint64_t vblank_alignment_dto_params; 335 uint8_t vblank_alignment_max_frame_time_diff; 336 bool is_asymmetric_memory; 337 bool is_single_rank_dimm; 338 bool use_pipe_ctx_sync_logic; 339 bool ignore_dpref_ss; 340 bool enable_mipi_converter_optimization; 341 }; 342 343 enum visual_confirm { 344 VISUAL_CONFIRM_DISABLE = 0, 345 VISUAL_CONFIRM_SURFACE = 1, 346 VISUAL_CONFIRM_HDR = 2, 347 VISUAL_CONFIRM_MPCTREE = 4, 348 VISUAL_CONFIRM_PSR = 5, 349 VISUAL_CONFIRM_SWIZZLE = 9, 350 }; 351 352 enum dc_psr_power_opts { 353 psr_power_opt_invalid = 0x0, 354 psr_power_opt_smu_opt_static_screen = 0x1, 355 psr_power_opt_z10_static_screen = 0x10, 356 psr_power_opt_ds_disable_allow = 0x100, 357 }; 358 359 enum dml_hostvm_override_opts { 360 DML_HOSTVM_NO_OVERRIDE = 0x0, 361 DML_HOSTVM_OVERRIDE_FALSE = 0x1, 362 DML_HOSTVM_OVERRIDE_TRUE = 0x2, 363 }; 364 365 enum dcc_option { 366 DCC_ENABLE = 0, 367 DCC_DISABLE = 1, 368 DCC_HALF_REQ_DISALBE = 2, 369 }; 370 371 enum pipe_split_policy { 372 MPC_SPLIT_DYNAMIC = 0, 373 MPC_SPLIT_AVOID = 1, 374 MPC_SPLIT_AVOID_MULT_DISP = 2, 375 }; 376 377 enum wm_report_mode { 378 WM_REPORT_DEFAULT = 0, 379 WM_REPORT_OVERRIDE = 1, 380 }; 381 enum dtm_pstate{ 382 dtm_level_p0 = 0,/*highest voltage*/ 383 dtm_level_p1, 384 dtm_level_p2, 385 dtm_level_p3, 386 dtm_level_p4,/*when active_display_count = 0*/ 387 }; 388 389 enum dcn_pwr_state { 390 DCN_PWR_STATE_UNKNOWN = -1, 391 DCN_PWR_STATE_MISSION_MODE = 0, 392 DCN_PWR_STATE_LOW_POWER = 3, 393 }; 394 395 enum dcn_zstate_support_state { 396 DCN_ZSTATE_SUPPORT_UNKNOWN, 397 DCN_ZSTATE_SUPPORT_ALLOW, 398 DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY, 399 DCN_ZSTATE_SUPPORT_DISALLOW, 400 }; 401 /* 402 * For any clocks that may differ per pipe 403 * only the max is stored in this structure 404 */ 405 struct dc_clocks { 406 int dispclk_khz; 407 int actual_dispclk_khz; 408 int dppclk_khz; 409 int actual_dppclk_khz; 410 int disp_dpp_voltage_level_khz; 411 int dcfclk_khz; 412 int socclk_khz; 413 int dcfclk_deep_sleep_khz; 414 int fclk_khz; 415 int phyclk_khz; 416 int dramclk_khz; 417 bool p_state_change_support; 418 enum dcn_zstate_support_state zstate_support; 419 bool dtbclk_en; 420 int ref_dtbclk_khz; 421 enum dcn_pwr_state pwr_state; 422 /* 423 * Elements below are not compared for the purposes of 424 * optimization required 425 */ 426 bool prev_p_state_change_support; 427 enum dtm_pstate dtm_level; 428 int max_supported_dppclk_khz; 429 int max_supported_dispclk_khz; 430 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 431 int bw_dispclk_khz; 432 }; 433 434 struct dc_bw_validation_profile { 435 bool enable; 436 437 unsigned long long total_ticks; 438 unsigned long long voltage_level_ticks; 439 unsigned long long watermark_ticks; 440 unsigned long long rq_dlg_ticks; 441 442 unsigned long long total_count; 443 unsigned long long skip_fast_count; 444 unsigned long long skip_pass_count; 445 unsigned long long skip_fail_count; 446 }; 447 448 #define BW_VAL_TRACE_SETUP() \ 449 unsigned long long end_tick = 0; \ 450 unsigned long long voltage_level_tick = 0; \ 451 unsigned long long watermark_tick = 0; \ 452 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 453 dm_get_timestamp(dc->ctx) : 0 454 455 #define BW_VAL_TRACE_COUNT() \ 456 if (dc->debug.bw_val_profile.enable) \ 457 dc->debug.bw_val_profile.total_count++ 458 459 #define BW_VAL_TRACE_SKIP(status) \ 460 if (dc->debug.bw_val_profile.enable) { \ 461 if (!voltage_level_tick) \ 462 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 463 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 464 } 465 466 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 467 if (dc->debug.bw_val_profile.enable) \ 468 voltage_level_tick = dm_get_timestamp(dc->ctx) 469 470 #define BW_VAL_TRACE_END_WATERMARKS() \ 471 if (dc->debug.bw_val_profile.enable) \ 472 watermark_tick = dm_get_timestamp(dc->ctx) 473 474 #define BW_VAL_TRACE_FINISH() \ 475 if (dc->debug.bw_val_profile.enable) { \ 476 end_tick = dm_get_timestamp(dc->ctx); \ 477 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 478 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 479 if (watermark_tick) { \ 480 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 481 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 482 } \ 483 } 484 485 union mem_low_power_enable_options { 486 struct { 487 bool vga: 1; 488 bool i2c: 1; 489 bool dmcu: 1; 490 bool dscl: 1; 491 bool cm: 1; 492 bool mpc: 1; 493 bool optc: 1; 494 bool vpg: 1; 495 bool afmt: 1; 496 } bits; 497 uint32_t u32All; 498 }; 499 500 union root_clock_optimization_options { 501 struct { 502 bool dpp: 1; 503 bool dsc: 1; 504 bool hdmistream: 1; 505 bool hdmichar: 1; 506 bool dpstream: 1; 507 bool symclk32_se: 1; 508 bool symclk32_le: 1; 509 bool symclk_fe: 1; 510 bool physymclk: 1; 511 bool dpiasymclk: 1; 512 uint32_t reserved: 22; 513 } bits; 514 uint32_t u32All; 515 }; 516 517 union dpia_debug_options { 518 struct { 519 uint32_t disable_dpia:1; /* bit 0 */ 520 uint32_t force_non_lttpr:1; /* bit 1 */ 521 uint32_t extend_aux_rd_interval:1; /* bit 2 */ 522 uint32_t disable_mst_dsc_work_around:1; /* bit 3 */ 523 uint32_t hpd_delay_in_ms:12; /* bits 4-15 */ 524 uint32_t disable_force_tbt3_work_around:1; /* bit 16 */ 525 uint32_t reserved:15; 526 } bits; 527 uint32_t raw; 528 }; 529 530 /* AUX wake work around options 531 * 0: enable/disable work around 532 * 1: use default timeout LINK_AUX_WAKE_TIMEOUT_MS 533 * 15-2: reserved 534 * 31-16: timeout in ms 535 */ 536 union aux_wake_wa_options { 537 struct { 538 uint32_t enable_wa : 1; 539 uint32_t use_default_timeout : 1; 540 uint32_t rsvd: 14; 541 uint32_t timeout_ms : 16; 542 } bits; 543 uint32_t raw; 544 }; 545 546 struct dc_debug_data { 547 uint32_t ltFailCount; 548 uint32_t i2cErrorCount; 549 uint32_t auxErrorCount; 550 }; 551 552 struct dc_phy_addr_space_config { 553 struct { 554 uint64_t start_addr; 555 uint64_t end_addr; 556 uint64_t fb_top; 557 uint64_t fb_offset; 558 uint64_t fb_base; 559 uint64_t agp_top; 560 uint64_t agp_bot; 561 uint64_t agp_base; 562 } system_aperture; 563 564 struct { 565 uint64_t page_table_start_addr; 566 uint64_t page_table_end_addr; 567 uint64_t page_table_base_addr; 568 bool base_addr_is_mc_addr; 569 } gart_config; 570 571 bool valid; 572 bool is_hvm_enabled; 573 uint64_t page_table_default_page_addr; 574 }; 575 576 struct dc_virtual_addr_space_config { 577 uint64_t page_table_base_addr; 578 uint64_t page_table_start_addr; 579 uint64_t page_table_end_addr; 580 uint32_t page_table_block_size_in_bytes; 581 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 582 }; 583 584 struct dc_bounding_box_overrides { 585 int sr_exit_time_ns; 586 int sr_enter_plus_exit_time_ns; 587 int urgent_latency_ns; 588 int percent_of_ideal_drambw; 589 int dram_clock_change_latency_ns; 590 int dummy_clock_change_latency_ns; 591 /* This forces a hard min on the DCFCLK we use 592 * for DML. Unlike the debug option for forcing 593 * DCFCLK, this override affects watermark calculations 594 */ 595 int min_dcfclk_mhz; 596 }; 597 598 struct dc_state; 599 struct resource_pool; 600 struct dce_hwseq; 601 602 struct dc_debug_options { 603 bool native422_support; 604 bool disable_dsc; 605 enum visual_confirm visual_confirm; 606 int visual_confirm_rect_height; 607 608 bool sanity_checks; 609 bool max_disp_clk; 610 bool surface_trace; 611 bool timing_trace; 612 bool clock_trace; 613 bool validation_trace; 614 bool bandwidth_calcs_trace; 615 int max_downscale_src_width; 616 617 /* stutter efficiency related */ 618 bool disable_stutter; 619 bool use_max_lb; 620 enum dcc_option disable_dcc; 621 enum pipe_split_policy pipe_split_policy; 622 bool force_single_disp_pipe_split; 623 bool voltage_align_fclk; 624 bool disable_min_fclk; 625 626 bool disable_dfs_bypass; 627 bool disable_dpp_power_gate; 628 bool disable_hubp_power_gate; 629 bool disable_dsc_power_gate; 630 int dsc_min_slice_height_override; 631 int dsc_bpp_increment_div; 632 bool disable_pplib_wm_range; 633 enum wm_report_mode pplib_wm_report_mode; 634 unsigned int min_disp_clk_khz; 635 unsigned int min_dpp_clk_khz; 636 unsigned int min_dram_clk_khz; 637 int sr_exit_time_dpm0_ns; 638 int sr_enter_plus_exit_time_dpm0_ns; 639 int sr_exit_time_ns; 640 int sr_enter_plus_exit_time_ns; 641 int urgent_latency_ns; 642 uint32_t underflow_assert_delay_us; 643 int percent_of_ideal_drambw; 644 int dram_clock_change_latency_ns; 645 bool optimized_watermark; 646 int always_scale; 647 bool disable_pplib_clock_request; 648 bool disable_clock_gate; 649 bool disable_mem_low_power; 650 bool pstate_enabled; 651 bool disable_dmcu; 652 bool disable_psr; 653 bool force_abm_enable; 654 bool disable_stereo_support; 655 bool vsr_support; 656 bool performance_trace; 657 bool az_endpoint_mute_only; 658 bool always_use_regamma; 659 bool recovery_enabled; 660 bool avoid_vbios_exec_table; 661 bool scl_reset_length10; 662 bool hdmi20_disable; 663 bool skip_detection_link_training; 664 uint32_t edid_read_retry_times; 665 bool remove_disconnect_edp; 666 unsigned int force_odm_combine; //bit vector based on otg inst 667 unsigned int seamless_boot_odm_combine; 668 unsigned int force_odm_combine_4to1; //bit vector based on otg inst 669 bool disable_z9_mpc; 670 unsigned int force_fclk_khz; 671 bool enable_tri_buf; 672 bool dmub_offload_enabled; 673 bool dmcub_emulation; 674 bool disable_idle_power_optimizations; 675 unsigned int mall_size_override; 676 unsigned int mall_additional_timer_percent; 677 bool mall_error_as_fatal; 678 bool dmub_command_table; /* for testing only */ 679 struct dc_bw_validation_profile bw_val_profile; 680 bool disable_fec; 681 bool disable_48mhz_pwrdwn; 682 /* This forces a hard min on the DCFCLK requested to SMU/PP 683 * watermarks are not affected. 684 */ 685 unsigned int force_min_dcfclk_mhz; 686 int dwb_fi_phase; 687 bool disable_timing_sync; 688 bool cm_in_bypass; 689 int force_clock_mode;/*every mode change.*/ 690 691 bool disable_dram_clock_change_vactive_support; 692 bool validate_dml_output; 693 bool enable_dmcub_surface_flip; 694 bool usbc_combo_phy_reset_wa; 695 bool disable_dsc_edp; 696 unsigned int force_dsc_edp_policy; 697 bool enable_dram_clock_change_one_display_vactive; 698 /* TODO - remove once tested */ 699 bool legacy_dp2_lt; 700 bool set_mst_en_for_sst; 701 bool disable_uhbr; 702 bool force_dp2_lt_fallback_method; 703 bool ignore_cable_id; 704 union mem_low_power_enable_options enable_mem_low_power; 705 union root_clock_optimization_options root_clock_optimization; 706 bool hpo_optimization; 707 bool force_vblank_alignment; 708 709 /* Enable dmub aux for legacy ddc */ 710 bool enable_dmub_aux_for_legacy_ddc; 711 bool optimize_edp_link_rate; /* eDP ILR */ 712 /* FEC/PSR1 sequence enable delay in 100us */ 713 uint8_t fec_enable_delay_in100us; 714 bool enable_driver_sequence_debug; 715 enum det_size crb_alloc_policy; 716 int crb_alloc_policy_min_disp_count; 717 bool disable_z10; 718 bool enable_z9_disable_interface; 719 bool enable_sw_cntl_psr; 720 union dpia_debug_options dpia_debug; 721 bool apply_vendor_specific_lttpr_wa; 722 bool extended_blank_optimization; 723 union aux_wake_wa_options aux_wake_wa; 724 /* uses value at boot and disables switch */ 725 bool disable_dtb_ref_clk_switch; 726 uint8_t psr_power_use_phy_fsm; 727 enum dml_hostvm_override_opts dml_hostvm_override; 728 }; 729 730 struct gpu_info_soc_bounding_box_v1_0; 731 struct dc { 732 struct dc_debug_options debug; 733 struct dc_versions versions; 734 struct dc_caps caps; 735 struct dc_cap_funcs cap_funcs; 736 struct dc_config config; 737 struct dc_bounding_box_overrides bb_overrides; 738 struct dc_bug_wa work_arounds; 739 struct dc_context *ctx; 740 struct dc_phy_addr_space_config vm_pa_config; 741 742 uint8_t link_count; 743 struct dc_link *links[MAX_PIPES * 2]; 744 745 struct dc_state *current_state; 746 struct resource_pool *res_pool; 747 748 struct clk_mgr *clk_mgr; 749 750 /* Display Engine Clock levels */ 751 struct dm_pp_clock_levels sclk_lvls; 752 753 /* Inputs into BW and WM calculations. */ 754 struct bw_calcs_dceip *bw_dceip; 755 struct bw_calcs_vbios *bw_vbios; 756 struct dcn_soc_bounding_box *dcn_soc; 757 struct dcn_ip_params *dcn_ip; 758 struct display_mode_lib dml; 759 760 /* HW functions */ 761 struct hw_sequencer_funcs hwss; 762 struct dce_hwseq *hwseq; 763 764 /* Require to optimize clocks and bandwidth for added/removed planes */ 765 bool optimized_required; 766 bool wm_optimized_required; 767 bool idle_optimizations_allowed; 768 bool enable_c20_dtm_b0; 769 770 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 771 772 /* FBC compressor */ 773 struct compressor *fbc_compressor; 774 775 struct dc_debug_data debug_data; 776 struct dpcd_vendor_signature vendor_signature; 777 778 const char *build_id; 779 struct vm_helper *vm_helper; 780 }; 781 782 enum frame_buffer_mode { 783 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 784 FRAME_BUFFER_MODE_ZFB_ONLY, 785 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 786 } ; 787 788 struct dchub_init_data { 789 int64_t zfb_phys_addr_base; 790 int64_t zfb_mc_base_addr; 791 uint64_t zfb_size_in_byte; 792 enum frame_buffer_mode fb_mode; 793 bool dchub_initialzied; 794 bool dchub_info_valid; 795 }; 796 797 struct dc_init_data { 798 struct hw_asic_id asic_id; 799 void *driver; /* ctx */ 800 struct cgs_device *cgs_device; 801 struct dc_bounding_box_overrides bb_overrides; 802 803 int num_virtual_links; 804 /* 805 * If 'vbios_override' not NULL, it will be called instead 806 * of the real VBIOS. Intended use is Diagnostics on FPGA. 807 */ 808 struct dc_bios *vbios_override; 809 enum dce_environment dce_environment; 810 811 struct dmub_offload_funcs *dmub_if; 812 struct dc_reg_helper_state *dmub_offload; 813 814 struct dc_config flags; 815 uint64_t log_mask; 816 817 struct dpcd_vendor_signature vendor_signature; 818 bool force_smu_not_present; 819 }; 820 821 struct dc_callback_init { 822 #ifdef CONFIG_DRM_AMD_DC_HDCP 823 struct cp_psp cp_psp; 824 #else 825 uint8_t reserved; 826 #endif 827 }; 828 829 struct dc *dc_create(const struct dc_init_data *init_params); 830 void dc_hardware_init(struct dc *dc); 831 832 int dc_get_vmid_use_vector(struct dc *dc); 833 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 834 /* Returns the number of vmids supported */ 835 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 836 void dc_init_callbacks(struct dc *dc, 837 const struct dc_callback_init *init_params); 838 void dc_deinit_callbacks(struct dc *dc); 839 void dc_destroy(struct dc **dc); 840 841 /******************************************************************************* 842 * Surface Interfaces 843 ******************************************************************************/ 844 845 enum { 846 TRANSFER_FUNC_POINTS = 1025 847 }; 848 849 struct dc_hdr_static_metadata { 850 /* display chromaticities and white point in units of 0.00001 */ 851 unsigned int chromaticity_green_x; 852 unsigned int chromaticity_green_y; 853 unsigned int chromaticity_blue_x; 854 unsigned int chromaticity_blue_y; 855 unsigned int chromaticity_red_x; 856 unsigned int chromaticity_red_y; 857 unsigned int chromaticity_white_point_x; 858 unsigned int chromaticity_white_point_y; 859 860 uint32_t min_luminance; 861 uint32_t max_luminance; 862 uint32_t maximum_content_light_level; 863 uint32_t maximum_frame_average_light_level; 864 }; 865 866 enum dc_transfer_func_type { 867 TF_TYPE_PREDEFINED, 868 TF_TYPE_DISTRIBUTED_POINTS, 869 TF_TYPE_BYPASS, 870 TF_TYPE_HWPWL 871 }; 872 873 struct dc_transfer_func_distributed_points { 874 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 875 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 876 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 877 878 uint16_t end_exponent; 879 uint16_t x_point_at_y1_red; 880 uint16_t x_point_at_y1_green; 881 uint16_t x_point_at_y1_blue; 882 }; 883 884 enum dc_transfer_func_predefined { 885 TRANSFER_FUNCTION_SRGB, 886 TRANSFER_FUNCTION_BT709, 887 TRANSFER_FUNCTION_PQ, 888 TRANSFER_FUNCTION_LINEAR, 889 TRANSFER_FUNCTION_UNITY, 890 TRANSFER_FUNCTION_HLG, 891 TRANSFER_FUNCTION_HLG12, 892 TRANSFER_FUNCTION_GAMMA22, 893 TRANSFER_FUNCTION_GAMMA24, 894 TRANSFER_FUNCTION_GAMMA26 895 }; 896 897 898 struct dc_transfer_func { 899 struct kref refcount; 900 enum dc_transfer_func_type type; 901 enum dc_transfer_func_predefined tf; 902 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 903 uint32_t sdr_ref_white_level; 904 union { 905 struct pwl_params pwl; 906 struct dc_transfer_func_distributed_points tf_pts; 907 }; 908 }; 909 910 911 union dc_3dlut_state { 912 struct { 913 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 914 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 915 uint32_t rmu_mux_num:3; /*index of mux to use*/ 916 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 917 uint32_t mpc_rmu1_mux:4; 918 uint32_t mpc_rmu2_mux:4; 919 uint32_t reserved:15; 920 } bits; 921 uint32_t raw; 922 }; 923 924 925 struct dc_3dlut { 926 struct kref refcount; 927 struct tetrahedral_params lut_3d; 928 struct fixed31_32 hdr_multiplier; 929 union dc_3dlut_state state; 930 }; 931 /* 932 * This structure is filled in by dc_surface_get_status and contains 933 * the last requested address and the currently active address so the called 934 * can determine if there are any outstanding flips 935 */ 936 struct dc_plane_status { 937 struct dc_plane_address requested_address; 938 struct dc_plane_address current_address; 939 bool is_flip_pending; 940 bool is_right_eye; 941 }; 942 943 union surface_update_flags { 944 945 struct { 946 uint32_t addr_update:1; 947 /* Medium updates */ 948 uint32_t dcc_change:1; 949 uint32_t color_space_change:1; 950 uint32_t horizontal_mirror_change:1; 951 uint32_t per_pixel_alpha_change:1; 952 uint32_t global_alpha_change:1; 953 uint32_t hdr_mult:1; 954 uint32_t rotation_change:1; 955 uint32_t swizzle_change:1; 956 uint32_t scaling_change:1; 957 uint32_t position_change:1; 958 uint32_t in_transfer_func_change:1; 959 uint32_t input_csc_change:1; 960 uint32_t coeff_reduction_change:1; 961 uint32_t output_tf_change:1; 962 uint32_t pixel_format_change:1; 963 uint32_t plane_size_change:1; 964 uint32_t gamut_remap_change:1; 965 966 /* Full updates */ 967 uint32_t new_plane:1; 968 uint32_t bpp_change:1; 969 uint32_t gamma_change:1; 970 uint32_t bandwidth_change:1; 971 uint32_t clock_change:1; 972 uint32_t stereo_format_change:1; 973 uint32_t lut_3d:1; 974 uint32_t full_update:1; 975 } bits; 976 977 uint32_t raw; 978 }; 979 980 struct dc_plane_state { 981 struct dc_plane_address address; 982 struct dc_plane_flip_time time; 983 bool triplebuffer_flips; 984 struct scaling_taps scaling_quality; 985 struct rect src_rect; 986 struct rect dst_rect; 987 struct rect clip_rect; 988 989 struct plane_size plane_size; 990 union dc_tiling_info tiling_info; 991 992 struct dc_plane_dcc_param dcc; 993 994 struct dc_gamma *gamma_correction; 995 struct dc_transfer_func *in_transfer_func; 996 struct dc_bias_and_scale *bias_and_scale; 997 struct dc_csc_transform input_csc_color_matrix; 998 struct fixed31_32 coeff_reduction_factor; 999 struct fixed31_32 hdr_mult; 1000 struct colorspace_transform gamut_remap_matrix; 1001 1002 // TODO: No longer used, remove 1003 struct dc_hdr_static_metadata hdr_static_ctx; 1004 1005 enum dc_color_space color_space; 1006 1007 struct dc_3dlut *lut3d_func; 1008 struct dc_transfer_func *in_shaper_func; 1009 struct dc_transfer_func *blend_tf; 1010 1011 struct dc_transfer_func *gamcor_tf; 1012 enum surface_pixel_format format; 1013 enum dc_rotation_angle rotation; 1014 enum plane_stereo_format stereo_format; 1015 1016 bool is_tiling_rotated; 1017 bool per_pixel_alpha; 1018 bool pre_multiplied_alpha; 1019 bool global_alpha; 1020 int global_alpha_value; 1021 bool visible; 1022 bool flip_immediate; 1023 bool horizontal_mirror; 1024 int layer_index; 1025 1026 union surface_update_flags update_flags; 1027 bool flip_int_enabled; 1028 bool skip_manual_trigger; 1029 1030 /* private to DC core */ 1031 struct dc_plane_status status; 1032 struct dc_context *ctx; 1033 1034 /* HACK: Workaround for forcing full reprogramming under some conditions */ 1035 bool force_full_update; 1036 1037 /* private to dc_surface.c */ 1038 enum dc_irq_source irq_source; 1039 struct kref refcount; 1040 }; 1041 1042 struct dc_plane_info { 1043 struct plane_size plane_size; 1044 union dc_tiling_info tiling_info; 1045 struct dc_plane_dcc_param dcc; 1046 enum surface_pixel_format format; 1047 enum dc_rotation_angle rotation; 1048 enum plane_stereo_format stereo_format; 1049 enum dc_color_space color_space; 1050 bool horizontal_mirror; 1051 bool visible; 1052 bool per_pixel_alpha; 1053 bool pre_multiplied_alpha; 1054 bool global_alpha; 1055 int global_alpha_value; 1056 bool input_csc_enabled; 1057 int layer_index; 1058 }; 1059 1060 struct dc_scaling_info { 1061 struct rect src_rect; 1062 struct rect dst_rect; 1063 struct rect clip_rect; 1064 struct scaling_taps scaling_quality; 1065 }; 1066 1067 struct dc_surface_update { 1068 struct dc_plane_state *surface; 1069 1070 /* isr safe update parameters. null means no updates */ 1071 const struct dc_flip_addrs *flip_addr; 1072 const struct dc_plane_info *plane_info; 1073 const struct dc_scaling_info *scaling_info; 1074 struct fixed31_32 hdr_mult; 1075 /* following updates require alloc/sleep/spin that is not isr safe, 1076 * null means no updates 1077 */ 1078 const struct dc_gamma *gamma; 1079 const struct dc_transfer_func *in_transfer_func; 1080 1081 const struct dc_csc_transform *input_csc_color_matrix; 1082 const struct fixed31_32 *coeff_reduction_factor; 1083 const struct dc_transfer_func *func_shaper; 1084 const struct dc_3dlut *lut3d_func; 1085 const struct dc_transfer_func *blend_tf; 1086 const struct colorspace_transform *gamut_remap_matrix; 1087 }; 1088 1089 /* 1090 * Create a new surface with default parameters; 1091 */ 1092 struct dc_plane_state *dc_create_plane_state(struct dc *dc); 1093 const struct dc_plane_status *dc_plane_get_status( 1094 const struct dc_plane_state *plane_state); 1095 1096 void dc_plane_state_retain(struct dc_plane_state *plane_state); 1097 void dc_plane_state_release(struct dc_plane_state *plane_state); 1098 1099 void dc_gamma_retain(struct dc_gamma *dc_gamma); 1100 void dc_gamma_release(struct dc_gamma **dc_gamma); 1101 struct dc_gamma *dc_create_gamma(void); 1102 1103 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 1104 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 1105 struct dc_transfer_func *dc_create_transfer_func(void); 1106 1107 struct dc_3dlut *dc_create_3dlut_func(void); 1108 void dc_3dlut_func_release(struct dc_3dlut *lut); 1109 void dc_3dlut_func_retain(struct dc_3dlut *lut); 1110 1111 void dc_post_update_surfaces_to_stream( 1112 struct dc *dc); 1113 1114 #include "dc_stream.h" 1115 1116 /* 1117 * Structure to store surface/stream associations for validation 1118 */ 1119 struct dc_validation_set { 1120 struct dc_stream_state *stream; 1121 struct dc_plane_state *plane_states[MAX_SURFACES]; 1122 uint8_t plane_count; 1123 }; 1124 1125 bool dc_validate_boot_timing(const struct dc *dc, 1126 const struct dc_sink *sink, 1127 struct dc_crtc_timing *crtc_timing); 1128 1129 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 1130 1131 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 1132 1133 bool dc_set_generic_gpio_for_stereo(bool enable, 1134 struct gpio_service *gpio_service); 1135 1136 /* 1137 * fast_validate: we return after determining if we can support the new state, 1138 * but before we populate the programming info 1139 */ 1140 enum dc_status dc_validate_global_state( 1141 struct dc *dc, 1142 struct dc_state *new_ctx, 1143 bool fast_validate); 1144 1145 1146 void dc_resource_state_construct( 1147 const struct dc *dc, 1148 struct dc_state *dst_ctx); 1149 1150 bool dc_acquire_release_mpc_3dlut( 1151 struct dc *dc, bool acquire, 1152 struct dc_stream_state *stream, 1153 struct dc_3dlut **lut, 1154 struct dc_transfer_func **shaper); 1155 1156 void dc_resource_state_copy_construct( 1157 const struct dc_state *src_ctx, 1158 struct dc_state *dst_ctx); 1159 1160 void dc_resource_state_copy_construct_current( 1161 const struct dc *dc, 1162 struct dc_state *dst_ctx); 1163 1164 void dc_resource_state_destruct(struct dc_state *context); 1165 1166 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 1167 1168 /* 1169 * TODO update to make it about validation sets 1170 * Set up streams and links associated to drive sinks 1171 * The streams parameter is an absolute set of all active streams. 1172 * 1173 * After this call: 1174 * Phy, Encoder, Timing Generator are programmed and enabled. 1175 * New streams are enabled with blank stream; no memory read. 1176 */ 1177 bool dc_commit_state(struct dc *dc, struct dc_state *context); 1178 1179 struct dc_state *dc_create_state(struct dc *dc); 1180 struct dc_state *dc_copy_state(struct dc_state *src_ctx); 1181 void dc_retain_state(struct dc_state *context); 1182 void dc_release_state(struct dc_state *context); 1183 1184 /******************************************************************************* 1185 * Link Interfaces 1186 ******************************************************************************/ 1187 1188 struct dpcd_caps { 1189 union dpcd_rev dpcd_rev; 1190 union max_lane_count max_ln_count; 1191 union max_down_spread max_down_spread; 1192 union dprx_feature dprx_feature; 1193 1194 /* valid only for eDP v1.4 or higher*/ 1195 uint8_t edp_supported_link_rates_count; 1196 enum dc_link_rate edp_supported_link_rates[8]; 1197 1198 /* dongle type (DP converter, CV smart dongle) */ 1199 enum display_dongle_type dongle_type; 1200 bool is_dongle_type_one; 1201 /* branch device or sink device */ 1202 bool is_branch_dev; 1203 /* Dongle's downstream count. */ 1204 union sink_count sink_count; 1205 bool is_mst_capable; 1206 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 1207 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 1208 struct dc_dongle_caps dongle_caps; 1209 1210 uint32_t sink_dev_id; 1211 int8_t sink_dev_id_str[6]; 1212 int8_t sink_hw_revision; 1213 int8_t sink_fw_revision[2]; 1214 1215 uint32_t branch_dev_id; 1216 int8_t branch_dev_name[6]; 1217 int8_t branch_hw_revision; 1218 int8_t branch_fw_revision[2]; 1219 1220 bool allow_invalid_MSA_timing_param; 1221 bool panel_mode_edp; 1222 bool dpcd_display_control_capable; 1223 bool ext_receiver_cap_field_present; 1224 bool dynamic_backlight_capable_edp; 1225 union dpcd_fec_capability fec_cap; 1226 struct dpcd_dsc_capabilities dsc_caps; 1227 struct dc_lttpr_caps lttpr_caps; 1228 struct dpcd_usb4_dp_tunneling_info usb4_dp_tun_info; 1229 1230 union dp_128b_132b_supported_link_rates dp_128b_132b_supported_link_rates; 1231 union dp_main_line_channel_coding_cap channel_coding_cap; 1232 union dp_sink_video_fallback_formats fallback_formats; 1233 union dp_fec_capability1 fec_cap1; 1234 union dp_cable_id cable_id; 1235 uint8_t edp_rev; 1236 union edp_alpm_caps alpm_caps; 1237 struct edp_psr_info psr_info; 1238 }; 1239 1240 union dpcd_sink_ext_caps { 1241 struct { 1242 /* 0 - Sink supports backlight adjust via PWM during SDR/HDR mode 1243 * 1 - Sink supports backlight adjust via AUX during SDR/HDR mode. 1244 */ 1245 uint8_t sdr_aux_backlight_control : 1; 1246 uint8_t hdr_aux_backlight_control : 1; 1247 uint8_t reserved_1 : 2; 1248 uint8_t oled : 1; 1249 uint8_t reserved : 3; 1250 } bits; 1251 uint8_t raw; 1252 }; 1253 1254 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1255 union hdcp_rx_caps { 1256 struct { 1257 uint8_t version; 1258 uint8_t reserved; 1259 struct { 1260 uint8_t repeater : 1; 1261 uint8_t hdcp_capable : 1; 1262 uint8_t reserved : 6; 1263 } byte0; 1264 } fields; 1265 uint8_t raw[3]; 1266 }; 1267 1268 union hdcp_bcaps { 1269 struct { 1270 uint8_t HDCP_CAPABLE:1; 1271 uint8_t REPEATER:1; 1272 uint8_t RESERVED:6; 1273 } bits; 1274 uint8_t raw; 1275 }; 1276 1277 struct hdcp_caps { 1278 union hdcp_rx_caps rx_caps; 1279 union hdcp_bcaps bcaps; 1280 }; 1281 #endif 1282 1283 #include "dc_link.h" 1284 1285 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); 1286 1287 /******************************************************************************* 1288 * Sink Interfaces - A sink corresponds to a display output device 1289 ******************************************************************************/ 1290 1291 struct dc_container_id { 1292 // 128bit GUID in binary form 1293 unsigned char guid[16]; 1294 // 8 byte port ID -> ELD.PortID 1295 unsigned int portId[2]; 1296 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 1297 unsigned short manufacturerName; 1298 // 2 byte product code -> ELD.ProductCode 1299 unsigned short productCode; 1300 }; 1301 1302 1303 struct dc_sink_dsc_caps { 1304 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 1305 // 'false' if they are sink's DSC caps 1306 bool is_virtual_dpcd_dsc; 1307 #if defined(CONFIG_DRM_AMD_DC_DCN) 1308 // 'true' if MST topology supports DSC passthrough for sink 1309 // 'false' if MST topology does not support DSC passthrough 1310 bool is_dsc_passthrough_supported; 1311 #endif 1312 struct dsc_dec_dpcd_caps dsc_dec_caps; 1313 }; 1314 1315 struct dc_sink_fec_caps { 1316 bool is_rx_fec_supported; 1317 bool is_topology_fec_supported; 1318 }; 1319 1320 /* 1321 * The sink structure contains EDID and other display device properties 1322 */ 1323 struct dc_sink { 1324 enum signal_type sink_signal; 1325 struct dc_edid dc_edid; /* raw edid */ 1326 struct dc_edid_caps edid_caps; /* parse display caps */ 1327 struct dc_container_id *dc_container_id; 1328 uint32_t dongle_max_pix_clk; 1329 void *priv; 1330 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 1331 bool converter_disable_audio; 1332 1333 struct dc_sink_dsc_caps dsc_caps; 1334 struct dc_sink_fec_caps fec_caps; 1335 1336 bool is_vsc_sdp_colorimetry_supported; 1337 1338 /* private to DC core */ 1339 struct dc_link *link; 1340 struct dc_context *ctx; 1341 1342 uint32_t sink_id; 1343 1344 /* private to dc_sink.c */ 1345 // refcount must be the last member in dc_sink, since we want the 1346 // sink structure to be logically cloneable up to (but not including) 1347 // refcount 1348 struct kref refcount; 1349 }; 1350 1351 void dc_sink_retain(struct dc_sink *sink); 1352 void dc_sink_release(struct dc_sink *sink); 1353 1354 struct dc_sink_init_data { 1355 enum signal_type sink_signal; 1356 struct dc_link *link; 1357 uint32_t dongle_max_pix_clk; 1358 bool converter_disable_audio; 1359 }; 1360 1361 bool dc_extended_blank_supported(struct dc *dc); 1362 1363 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 1364 1365 /* Newer interfaces */ 1366 struct dc_cursor { 1367 struct dc_plane_address address; 1368 struct dc_cursor_attributes attributes; 1369 }; 1370 1371 1372 /******************************************************************************* 1373 * Interrupt interfaces 1374 ******************************************************************************/ 1375 enum dc_irq_source dc_interrupt_to_irq_source( 1376 struct dc *dc, 1377 uint32_t src_id, 1378 uint32_t ext_id); 1379 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 1380 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 1381 enum dc_irq_source dc_get_hpd_irq_source_at_index( 1382 struct dc *dc, uint32_t link_index); 1383 1384 void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable); 1385 1386 /******************************************************************************* 1387 * Power Interfaces 1388 ******************************************************************************/ 1389 1390 void dc_set_power_state( 1391 struct dc *dc, 1392 enum dc_acpi_cm_power_state power_state); 1393 void dc_resume(struct dc *dc); 1394 1395 void dc_power_down_on_boot(struct dc *dc); 1396 1397 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1398 /* 1399 * HDCP Interfaces 1400 */ 1401 enum hdcp_message_status dc_process_hdcp_msg( 1402 enum signal_type signal, 1403 struct dc_link *link, 1404 struct hdcp_protection_message *message_info); 1405 #endif 1406 bool dc_is_dmcu_initialized(struct dc *dc); 1407 1408 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 1409 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 1410 1411 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane, 1412 struct dc_cursor_attributes *cursor_attr); 1413 1414 void dc_allow_idle_optimizations(struct dc *dc, bool allow); 1415 1416 /* 1417 * blank all streams, and set min and max memory clock to 1418 * lowest and highest DPM level, respectively 1419 */ 1420 void dc_unlock_memory_clock_frequency(struct dc *dc); 1421 1422 /* 1423 * set min memory clock to the min required for current mode, 1424 * max to maxDPM, and unblank streams 1425 */ 1426 void dc_lock_memory_clock_frequency(struct dc *dc); 1427 1428 /* set soft max for memclk, to be used for AC/DC switching clock limitations */ 1429 void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable); 1430 1431 /* cleanup on driver unload */ 1432 void dc_hardware_release(struct dc *dc); 1433 1434 bool dc_set_psr_allow_active(struct dc *dc, bool enable); 1435 void dc_z10_restore(const struct dc *dc); 1436 void dc_z10_save_init(struct dc *dc); 1437 1438 bool dc_is_dmub_outbox_supported(struct dc *dc); 1439 bool dc_enable_dmub_notifications(struct dc *dc); 1440 1441 void dc_enable_dmub_outbox(struct dc *dc); 1442 1443 bool dc_process_dmub_aux_transfer_async(struct dc *dc, 1444 uint32_t link_index, 1445 struct aux_payload *payload); 1446 1447 /* Get dc link index from dpia port index */ 1448 uint8_t get_link_index_from_dpia_port_index(const struct dc *dc, 1449 uint8_t dpia_port_index); 1450 1451 bool dc_process_dmub_set_config_async(struct dc *dc, 1452 uint32_t link_index, 1453 struct set_config_cmd_payload *payload, 1454 struct dmub_notification *notify); 1455 1456 enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc, 1457 uint32_t link_index, 1458 uint8_t mst_alloc_slots, 1459 uint8_t *mst_slots_in_use); 1460 1461 /******************************************************************************* 1462 * DSC Interfaces 1463 ******************************************************************************/ 1464 #include "dc_dsc.h" 1465 1466 /******************************************************************************* 1467 * Disable acc mode Interfaces 1468 ******************************************************************************/ 1469 void dc_disable_accelerated_mode(struct dc *dc); 1470 1471 #endif /* DC_INTERFACE_H_ */ 1472