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Searched refs:dsi_phy_write_udelay (Results 1 – 3 of 3) sorted by relevance

/linux-5.19.10/drivers/gpu/drm/msm/dsi/phy/
Ddsi_phy_28nm.c106 dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_TEST_CFG, in pll_28nm_software_reset()
108 dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_TEST_CFG, 0x00, 1); in pll_28nm_software_reset()
305 dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 1); in _dsi_pll_28nm_vco_prepare_hpm()
308 dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200); in _dsi_pll_28nm_vco_prepare_hpm()
311 dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500); in _dsi_pll_28nm_vco_prepare_hpm()
314 dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 600); in _dsi_pll_28nm_vco_prepare_hpm()
318 dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, in _dsi_pll_28nm_vco_prepare_hpm()
335 dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 1); in _dsi_pll_28nm_vco_prepare_hpm()
338 dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200); in _dsi_pll_28nm_vco_prepare_hpm()
341 dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 250); in _dsi_pll_28nm_vco_prepare_hpm()
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Ddsi_phy.h17 #define dsi_phy_write_udelay(offset, data, delay_us) { msm_writel((data), (offset)); udelay(delay_u… macro
Ddsi_phy_14nm.c375 dsi_phy_write_udelay(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0x20, 10); in pll_14nm_software_reset()