Searched refs:dsi_phy_read (Results 1 – 7 of 7) sorted by relevance
77 val = dsi_phy_read(pll_28nm->phy->pll_base + REG_DSI_28nm_8960_PHY_PLL_RDY); in pll_28nm_poll_for_ready()109 val = dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_2); in dsi_pll_28nm_clk_set_rate()116 val = dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3); in dsi_pll_28nm_clk_set_rate()126 val = dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8); in dsi_pll_28nm_clk_set_rate()152 status = dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_0); in dsi_pll_28nm_clk_recalc_rate()155 fb_divider = dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_1); in dsi_pll_28nm_clk_recalc_rate()157 temp = dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_2) & 0x07; in dsi_pll_28nm_clk_recalc_rate()161 ref_divider = dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3); in dsi_pll_28nm_clk_recalc_rate()198 val = dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9); in dsi_pll_28nm_vco_prepare()202 val = dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8); in dsi_pll_28nm_vco_prepare()[all …]
312 u32 data = dsi_phy_read(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0); in dsi_pll_disable_pll_bias()321 u32 data = dsi_phy_read(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0); in dsi_pll_enable_pll_bias()332 data = dsi_phy_read(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1); in dsi_pll_disable_global_clk()342 data = dsi_phy_read(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1); in dsi_pll_enable_global_clk()443 dec = dsi_phy_read(base + REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1); in dsi_pll_7nm_vco_recalc_rate()446 frac = dsi_phy_read(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1); in dsi_pll_7nm_vco_recalc_rate()447 frac |= ((dsi_phy_read(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1) & in dsi_pll_7nm_vco_recalc_rate()449 frac |= ((dsi_phy_read(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1) & in dsi_pll_7nm_vco_recalc_rate()502 cached->pll_out_div = dsi_phy_read(pll_7nm->phy->pll_base + in dsi_7nm_pll_save_state()506 cmn_clk_cfg0 = dsi_phy_read(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG0); in dsi_7nm_pll_save_state()[all …]
305 u32 data = dsi_phy_read(pll->phy->base + REG_DSI_10nm_PHY_CMN_CTRL_0); in dsi_pll_disable_pll_bias()315 u32 data = dsi_phy_read(pll->phy->base + REG_DSI_10nm_PHY_CMN_CTRL_0); in dsi_pll_enable_pll_bias()327 data = dsi_phy_read(pll->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG1); in dsi_pll_disable_global_clk()336 data = dsi_phy_read(pll->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG1); in dsi_pll_enable_global_clk()429 dec = dsi_phy_read(base + REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1); in dsi_pll_10nm_vco_recalc_rate()432 frac = dsi_phy_read(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1); in dsi_pll_10nm_vco_recalc_rate()433 frac |= ((dsi_phy_read(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1) & in dsi_pll_10nm_vco_recalc_rate()435 frac |= ((dsi_phy_read(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1) & in dsi_pll_10nm_vco_recalc_rate()488 cached->pll_out_div = dsi_phy_read(pll_10nm->phy->pll_base + in dsi_10nm_pll_save_state()492 cmn_clk_cfg0 = dsi_phy_read(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG0); in dsi_10nm_pll_save_state()[all …]
85 val = dsi_phy_read(pll_28nm->phy->pll_base + REG_DSI_28nm_PHY_PLL_STATUS); in pll_28nm_poll_for_ready()170 sdm_cfg1 = dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1); in dsi_pll_28nm_clk_set_rate()252 doubler = dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG) & in dsi_pll_28nm_clk_recalc_rate()257 sdm0 = dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0); in dsi_pll_28nm_clk_recalc_rate()261 dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0), in dsi_pll_28nm_clk_recalc_rate()267 dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1), in dsi_pll_28nm_clk_recalc_rate()270 sdm2 = FIELD(dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG2), in dsi_pll_28nm_clk_recalc_rate()272 sdm3 = FIELD(dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG3), in dsi_pll_28nm_clk_recalc_rate()485 dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG); in dsi_28nm_pll_save_state()487 dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG); in dsi_28nm_pll_save_state()[all …]
119 val = dsi_phy_read(base + REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS); in pll_14nm_poll_for_ready()133 val = dsi_phy_read(base + REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS); in pll_14nm_poll_for_ready()500 dec_start = dsi_phy_read(base + REG_DSI_14nm_PHY_PLL_DEC_START); in dsi_pll_14nm_vco_recalc_rate()505 div_frac_start = (dsi_phy_read(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3) in dsi_pll_14nm_vco_recalc_rate()507 div_frac_start |= (dsi_phy_read(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2) in dsi_pll_14nm_vco_recalc_rate()509 div_frac_start |= dsi_phy_read(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1) in dsi_pll_14nm_vco_recalc_rate()611 val = dsi_phy_read(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0) >> shift; in dsi_pll_14nm_postdiv_recalc_rate()653 val = dsi_phy_read(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0); in dsi_pll_14nm_postdiv_set_rate()691 data = dsi_phy_read(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0); in dsi_14nm_pll_save_state()999 glbl_test_ctrl = dsi_phy_read(base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL); in dsi_14nm_phy_enable()
15 #define dsi_phy_read(offset) msm_readl((offset)) macro
88 val = dsi_phy_read(base + REG_DSI_20nm_PHY_GLBL_TEST_CTRL); in dsi_20nm_phy_enable()