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Searched refs:drvsel (Results 1 – 2 of 2) sorted by relevance

/linux-5.19.10/drivers/clk/socfpga/
Dclk.h23 #define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \ argument
24 ((((smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0))
26 #define SYSMGR_SDMMC_CTRL_SET_AS10(smplsel, drvsel) \ argument
27 ((((smplsel) & 0x7) << 4) | (((drvsel) & 0x7) << 0))
/linux-5.19.10/Documentation/devicetree/bindings/clock/
Daltr_socfpga.txt28 value is the cclk_in_drv(drvsel). The clk-phase is used to enable the correct