Home
last modified time | relevance | path

Searched refs:dpll (Results 1 – 25 of 70) sorted by relevance

123

/linux-5.19.10/drivers/gpu/drm/i915/display/
Dintel_dpll.c310 int pnv_calc_dpll_params(int refclk, struct dpll *clock) in pnv_calc_dpll_params()
322 static u32 i9xx_dpll_compute_m(const struct dpll *dpll) in i9xx_dpll_compute_m() argument
324 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); in i9xx_dpll_compute_m()
327 int i9xx_calc_dpll_params(int refclk, struct dpll *clock) in i9xx_calc_dpll_params()
339 int vlv_calc_dpll_params(int refclk, struct dpll *clock) in vlv_calc_dpll_params()
351 int chv_calc_dpll_params(int refclk, struct dpll *clock) in chv_calc_dpll_params()
370 const struct dpll *clock) in intel_pll_is_valid()
441 const struct dpll *match_clock, in i9xx_find_best_dpll()
442 struct dpll *best_clock) in i9xx_find_best_dpll()
445 struct dpll clock; in i9xx_find_best_dpll()
[all …]
Dintel_dpll.h11 struct dpll;
23 int vlv_calc_dpll_params(int refclk, struct dpll *clock);
24 int pnv_calc_dpll_params(int refclk, struct dpll *clock);
25 int i9xx_calc_dpll_params(int refclk, struct dpll *clock);
26 u32 i9xx_dpll_compute_fp(const struct dpll *dpll);
31 const struct dpll *dpll);
41 struct dpll *best_clock);
42 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
Dintel_dpll_mgr.c113 for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) { in intel_atomic_duplicate_dpll_state()
114 struct intel_shared_dpll *pll = &dev_priv->dpll.shared_dplls[i]; in intel_atomic_duplicate_dpll_state()
149 return &dev_priv->dpll.shared_dplls[id]; in intel_get_shared_dpll_by_id()
164 long pll_idx = pll - dev_priv->dpll.shared_dplls; in intel_get_shared_dpll_id()
168 pll_idx >= dev_priv->dpll.num_shared_dpll)) in intel_get_shared_dpll_id()
245 mutex_lock(&dev_priv->dpll.lock); in intel_enable_shared_dpll()
271 mutex_unlock(&dev_priv->dpll.lock); in intel_enable_shared_dpll()
294 mutex_lock(&dev_priv->dpll.lock); in intel_disable_shared_dpll()
317 mutex_unlock(&dev_priv->dpll.lock); in intel_disable_shared_dpll()
336 pll = &dev_priv->dpll.shared_dplls[i]; in intel_find_shared_dpll()
[all …]
Dintel_dvo.c429 u32 dpll[I915_MAX_PIPES]; in intel_dvo_init() local
466 dpll[pipe] = intel_de_read(dev_priv, DPLL(pipe)); in intel_dvo_init()
468 dpll[pipe] | DPLL_DVO_2X_MODE); in intel_dvo_init()
475 intel_de_write(dev_priv, DPLL(pipe), dpll[pipe]); in intel_dvo_init()
Dg4x_dp.h20 const struct dpll *vlv_get_dpll(struct drm_i915_private *i915);
Dg4x_dp.c28 static const struct dpll g4x_dpll[] = {
33 static const struct dpll pch_dpll[] = {
38 static const struct dpll vlv_dpll[] = {
43 static const struct dpll chv_dpll[] = {
49 const struct dpll *vlv_get_dpll(struct drm_i915_private *i915) in vlv_get_dpll()
58 const struct dpll *divisor = NULL; in g4x_dp_set_clock()
78 pipe_config->dpll = divisor[i]; in g4x_dp_set_clock()
/linux-5.19.10/drivers/gpu/drm/gma500/
Dpsb_intel_display.c106 u32 dpll = 0, fp = 0, dspcntr, pipeconf; in psb_intel_crtc_mode_set() local
157 dpll = DPLL_VGA_MODE_DIS; in psb_intel_crtc_mode_set()
159 dpll |= DPLLB_MODE_LVDS; in psb_intel_crtc_mode_set()
160 dpll |= DPLL_DVO_HIGH_SPEED; in psb_intel_crtc_mode_set()
162 dpll |= DPLLB_MODE_DAC_SERIAL; in psb_intel_crtc_mode_set()
166 dpll |= DPLL_DVO_HIGH_SPEED; in psb_intel_crtc_mode_set()
167 dpll |= in psb_intel_crtc_mode_set()
172 dpll |= (1 << (clock.p1 - 1)) << 16; in psb_intel_crtc_mode_set()
175 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; in psb_intel_crtc_mode_set()
178 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; in psb_intel_crtc_mode_set()
[all …]
Doaktrail_crtc.c243 temp = REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
245 REG_WRITE_WITH_AUX(map->dpll, temp, i); in oaktrail_crtc_dpms()
246 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
249 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
251 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
254 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
256 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
315 temp = REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
317 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
319 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
[all …]
Dcdv_intel_display.c583 u32 dpll = 0, dspcntr, pipeconf; in cdv_intel_crtc_mode_set() local
664 dpll = DPLL_VGA_MODE_DIS; in cdv_intel_crtc_mode_set()
675 dpll |= DPLL_SYNCLOCK_ENABLE; in cdv_intel_crtc_mode_set()
721 REG_WRITE(map->dpll, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE); in cdv_intel_crtc_mode_set()
722 REG_READ(map->dpll); in cdv_intel_crtc_mode_set()
757 dpll |= DPLL_VCO_ENABLE; in cdv_intel_crtc_mode_set()
766 REG_WRITE(map->dpll, in cdv_intel_crtc_mode_set()
767 (REG_READ(map->dpll) & ~DPLL_LOCK) | DPLL_VCO_ENABLE); in cdv_intel_crtc_mode_set()
768 REG_READ(map->dpll); in cdv_intel_crtc_mode_set()
772 if (!(REG_READ(map->dpll) & DPLL_LOCK)) { in cdv_intel_crtc_mode_set()
[all …]
Dgma_display.c220 temp = REG_READ(map->dpll); in gma_crtc_dpms()
222 REG_WRITE(map->dpll, temp); in gma_crtc_dpms()
223 REG_READ(map->dpll); in gma_crtc_dpms()
226 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in gma_crtc_dpms()
227 REG_READ(map->dpll); in gma_crtc_dpms()
230 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in gma_crtc_dpms()
231 REG_READ(map->dpll); in gma_crtc_dpms()
308 temp = REG_READ(map->dpll); in gma_crtc_dpms()
310 REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE); in gma_crtc_dpms()
311 REG_READ(map->dpll); in gma_crtc_dpms()
[all …]
Doaktrail_hdmi.c282 u32 dspcntr, pipeconf, dpll, temp; in oaktrail_crtc_hdmi_mode_set() local
292 dpll = REG_READ(DPLL_CTRL); in oaktrail_crtc_hdmi_mode_set()
293 if ((dpll & DPLL_PWRDN) == 0) { in oaktrail_crtc_hdmi_mode_set()
294 REG_WRITE(DPLL_CTRL, dpll | (DPLL_PWRDN | DPLL_RESET)); in oaktrail_crtc_hdmi_mode_set()
308 dpll = REG_READ(DPLL_CTRL); in oaktrail_crtc_hdmi_mode_set()
309 dpll &= ~DPLL_PDIV_MASK; in oaktrail_crtc_hdmi_mode_set()
310 dpll &= ~(DPLL_PWRDN | DPLL_RESET); in oaktrail_crtc_hdmi_mode_set()
314 REG_WRITE(DPLL_CTRL, (dpll | (clock.np << DPLL_PDIV_SHIFT) | DPLL_ENSTAT | DPLL_DITHEN)); in oaktrail_crtc_hdmi_mode_set()
Doaktrail_device.c199 p->dpll = PSB_RVDC32(MRST_DPLL_A); in oaktrail_save_display_registers()
316 PSB_WVDC32(p->dpll, MRST_DPLL_A); in oaktrail_restore_display_registers()
457 .dpll = MRST_DPLL_A,
481 .dpll = DPLL_B,
/linux-5.19.10/Documentation/devicetree/bindings/clock/ti/
Ddpll.txt18 "ti,omap3-dpll-clock",
19 "ti,omap3-dpll-core-clock",
20 "ti,omap3-dpll-per-clock",
21 "ti,omap3-dpll-per-j-type-clock",
22 "ti,omap4-dpll-clock",
23 "ti,omap4-dpll-x2-clock",
24 "ti,omap4-dpll-core-clock",
25 "ti,omap4-dpll-m4xen-clock",
26 "ti,omap4-dpll-j-type-clock",
27 "ti,omap5-mpu-dpll-clock",
[all …]
/linux-5.19.10/Documentation/devicetree/bindings/media/i2c/
Dadv748x.yaml38 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ]
39 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ]
40 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ]
41 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ]
42 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ]
43 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ]
44 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ]
45 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ]
46 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ]
47 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ]
[all …]
/linux-5.19.10/arch/arm/boot/dts/
Ddra7xx-clocks.dtsi229 compatible = "ti,omap4-dpll-m4xen-clock";
235 dpll_abe_x2_ck: clock-dpll-abe-x2 {
237 compatible = "ti,omap4-dpll-x2-clock";
242 dpll_abe_m2x2_ck: clock-dpll-abe-m2x2-8@1f0 {
264 dpll_abe_m2_ck: clock-dpll-abe-m2-8@1f0 {
276 dpll_abe_m3x2_ck: clock-dpll-abe-m3x2-8@1f4 {
288 dpll_core_byp_mux: clock-dpll-core-byp-mux-23@12c {
299 compatible = "ti,omap4-dpll-core-clock";
305 dpll_core_x2_ck: clock-dpll-core-x2 {
307 compatible = "ti,omap4-dpll-x2-clock";
[all …]
Dam43xx-clocks.dtsi231 compatible = "ti,am3-dpll-core-clock";
237 dpll_core_x2_ck: clock-dpll-core-x2 {
239 compatible = "ti,am3-dpll-x2-clock";
244 dpll_core_m4_ck: clock-dpll-core-m4-8@2d38 {
256 dpll_core_m5_ck: clock-dpll-core-m5-8@2d3c {
268 dpll_core_m6_ck: clock-dpll-core-m6-8@2d40 {
282 compatible = "ti,am3-dpll-clock";
288 dpll_mpu_m2_ck: clock-dpll-mpu-m2-8@2d70 {
311 compatible = "ti,am3-dpll-clock";
317 dpll_ddr_m2_ck: clock-dpll-ddr-m2-8@2db0 {
[all …]
Dam33xx-clocks.dtsi190 compatible = "ti,am3-dpll-core-clock";
196 dpll_core_x2_ck: clock-dpll-core-x2 {
198 compatible = "ti,am3-dpll-x2-clock";
203 dpll_core_m4_ck: clock-dpll-core-m4@480 {
213 dpll_core_m5_ck: clock-dpll-core-m5@484 {
223 dpll_core_m6_ck: clock-dpll-core-m6@4d8 {
235 compatible = "ti,am3-dpll-clock";
241 dpll_mpu_m2_ck: clock-dpll-mpu-m2@4a8 {
253 compatible = "ti,am3-dpll-no-gate-clock";
259 dpll_ddr_m2_ck: clock-dpll-ddr-m2@4a0 {
[all …]
Domap54xx-clocks.dtsi119 compatible = "ti,omap4-dpll-m4xen-clock";
127 compatible = "ti,omap4-dpll-x2-clock";
201 compatible = "ti,omap4-dpll-core-clock";
209 compatible = "ti,omap4-dpll-x2-clock";
352 compatible = "ti,omap4-dpll-clock";
362 compatible = "ti,omap4-dpll-x2-clock";
402 compatible = "ti,omap5-mpu-dpll-clock";
586 compatible = "ti,omap4-dpll-clock";
594 compatible = "ti,omap4-dpll-x2-clock";
661 compatible = "ti,omap4-dpll-clock";
[all …]
/linux-5.19.10/arch/arm/mach-omap1/
Dsram.S36 strh r0, [r2] @ set dpll into bypass mode
41 strh r0, [r2] @ write new dpll value
49 lock: ldrh r4, [r2], #0 @ read back dpll value
52 tst r4, #1 << 0 @ dpll rate locked?
/linux-5.19.10/Documentation/devicetree/bindings/clock/
Dmicrochip,sparx5-dpll.yaml4 $id: http://devicetree.org/schemas/clock/microchip,sparx5-dpll.yaml#
18 const: microchip,sparx5-dpll
46 compatible = "microchip,sparx5-dpll";
/linux-5.19.10/drivers/ata/
Dpata_hpt3x2n.c312 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); in hpt3x2n_qc_defer() local
319 if ((flags & USE_DPLL) != dpll && alt->qc_active) in hpt3x2n_qc_defer()
328 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); in hpt3x2n_qc_issue() local
330 if ((flags & USE_DPLL) != dpll) { in hpt3x2n_qc_issue()
332 flags |= dpll; in hpt3x2n_qc_issue()
335 hpt3x2n_set_clock(ap, dpll ? 0x21 : 0x23); in hpt3x2n_qc_issue()
Dpata_hpt37x.c943 int dpll, adjust; in hpt37x_init_one() local
946 dpll = (ppi[0]->udma_mask & 0xC0) ? 3 : 2; in hpt37x_init_one()
948 f_low = (MHz[clock_slot] * 48) / MHz[dpll]; in hpt37x_init_one()
976 if (dpll == 3) in hpt37x_init_one()
982 MHz[clock_slot], MHz[dpll]); in hpt37x_init_one()
/linux-5.19.10/drivers/gpu/drm/rcar-du/
Drcar_du_crtc.c85 struct dpll_info *dpll, in rcar_du_dpll_divider() argument
149 dpll->n = n; in rcar_du_dpll_divider()
150 dpll->m = m; in rcar_du_dpll_divider()
151 dpll->fdpll = fdpll; in rcar_du_dpll_divider()
152 dpll->output = output; in rcar_du_dpll_divider()
164 dpll->output, dpll->fdpll, dpll->n, dpll->m, best_diff); in rcar_du_dpll_divider()
224 struct dpll_info dpll = { 0 }; in rcar_du_crtc_set_display_timing() local
248 rcar_du_dpll_divider(rcrtc, &dpll, extclk, target); in rcar_du_crtc_set_display_timing()
251 | DPLLCR_FDPLL(dpll.fdpll) in rcar_du_crtc_set_display_timing()
252 | DPLLCR_N(dpll.n) | DPLLCR_M(dpll.m) in rcar_du_crtc_set_display_timing()
/linux-5.19.10/drivers/video/fbdev/intelfb/
Dintelfbhw.c682 static void intelfbhw_get_p1p2(struct intelfb_info *dinfo, int dpll, in intelfbhw_get_p1p2() argument
688 if (dpll & DPLL_P1_FORCE_DIV2) in intelfbhw_get_p1p2()
691 p1 = (dpll >> DPLL_P1_SHIFT) & 0xff; in intelfbhw_get_p1p2()
695 p2 = (dpll >> DPLL_I9XX_P2_SHIFT) & DPLL_P2_MASK; in intelfbhw_get_p1p2()
697 if (dpll & DPLL_P1_FORCE_DIV2) in intelfbhw_get_p1p2()
700 p1 = (dpll >> DPLL_P1_SHIFT) & DPLL_P1_MASK; in intelfbhw_get_p1p2()
701 p2 = (dpll >> DPLL_P2_SHIFT) & DPLL_P2_MASK; in intelfbhw_get_p1p2()
1043 u32 *dpll, *fp0, *fp1; in intelfbhw_mode_to_hw() local
1058 dpll = &hw->dpll_b; in intelfbhw_mode_to_hw()
1070 dpll = &hw->dpll_a; in intelfbhw_mode_to_hw()
[all …]
/linux-5.19.10/arch/arm64/boot/dts/sprd/
Dsharkl3.dtsi123 dpll: dpll { label
124 compatible = "sprd,sc9863a-dpll";

123