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Searched refs:div_width (Results 1 – 14 of 14) sorted by relevance

/linux-5.19.10/drivers/clk/rockchip/
Dclk.h408 int div_shift, int div_width,
453 u8 div_width; member
476 .div_width = dw, \
498 .div_width = dw, \
516 .div_width = dw, \
534 .div_width = dw, \
574 .div_width = dw, \
593 .div_width = dw, \
609 .div_width = 16, \
626 .div_width = 16, \
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Dclk-ddr.c22 int div_width; member
94 int div_shift, int div_width, in rockchip_clk_register_ddrclk() argument
130 ddrclk->div_width = div_width; in rockchip_clk_register_ddrclk()
Dclk.c43 int div_offset, u8 div_shift, u8 div_width, u8 div_flags, in rockchip_clk_register_branch() argument
84 if (div_width > 0) { in rockchip_clk_register_branch()
97 div->width = div_width; in rockchip_clk_register_branch()
466 list->div_shift, list->div_width, in rockchip_clk_register_branches()
473 list->div_shift, list->div_width, in rockchip_clk_register_branches()
491 list->div_width, list->div_flags, in rockchip_clk_register_branches()
509 list->div_offset, list->div_shift, list->div_width, in rockchip_clk_register_branches()
533 list->div_shift, list->div_width, in rockchip_clk_register_branches()
543 list->div_width, list->div_flags, in rockchip_clk_register_branches()
Dclk-half-divider.c163 u8 div_shift, u8 div_width, in rockchip_clk_register_halfdiv() argument
202 if (div_width > 0) { in rockchip_clk_register_halfdiv()
210 div->width = div_width; in rockchip_clk_register_halfdiv()
/linux-5.19.10/drivers/clk/x86/
Dclk-cgu.h188 u8 div_width; member
236 .div_width = _width, \
276 .div_width = _width, \
296 .div_width = _width, \
Dclk-cgu.c32 list->div_width, list->div_val); in lgm_clk_register_fixed()
221 u8 width = list->div_width; in lgm_clk_register_divider()
279 list->div_width, list->div_val); in lgm_clk_register_fixed_factor()
/linux-5.19.10/drivers/clk/mediatek/
Dclk-mtk.h164 unsigned char div_width; member
175 .div_width = _width, \
Dclk-mt8167.c664 .div_width = _width, \
694 .div_width = _width, \
Dclk-mtk.c376 mcd->div_width, mcd->clk_divider_flags, lock); in mtk_clk_register_dividers()
Dclk-mt8516.c474 .div_width = _width, \
/linux-5.19.10/drivers/clk/socfpga/
Dclk-gate-s10.c152 socfpga_clk->width = clks->div_width; in s10_register_gate()
210 socfpga_clk->width = clks->div_width; in agilex_register_gate()
Dstratix10-clk.h68 u8 div_width; member
/linux-5.19.10/drivers/clk/
Dclk-bm1880.c121 s8 div_width; member
153 .div_width = _div_width, \
813 div_hws->div.width = clks->div_width; in bm1880_clk_register_composite()
Dclk-k210.c37 u8 div_width; member
57 .div_width = (_width), \
759 div_val = (reg >> cfg->div_shift) & GENMASK(cfg->div_width - 1, 0); in k210_clk_get_rate()