Searched refs:div_ctl0 (Results 1 – 1 of 1) sorted by relevance
355 u32 gnrl_ctl, div_ctl0; in clk_pll1443x_set_rate() local360 div_ctl0 = readl_relaxed(pll->base + DIV_CTL0); in clk_pll1443x_set_rate()362 if (!clk_pll14xx_mp_change(&rate, div_ctl0)) { in clk_pll1443x_set_rate()364 div_ctl0 &= ~SDIV_MASK; in clk_pll1443x_set_rate()365 div_ctl0 |= FIELD_PREP(SDIV_MASK, rate.sdiv); in clk_pll1443x_set_rate()366 writel_relaxed(div_ctl0, pll->base + DIV_CTL0); in clk_pll1443x_set_rate()383 div_ctl0 = FIELD_PREP(MDIV_MASK, rate.mdiv) | in clk_pll1443x_set_rate()386 writel_relaxed(div_ctl0, pll->base + DIV_CTL0); in clk_pll1443x_set_rate()